AM79C874VC AMD (ADVANCED MICRO DEVICES), AM79C874VC Datasheet - Page 18

• Manufacturer Part Number: AM79C874VC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C874VC

• Lead Free Status / RoHS Status: Not Compliant

For 100BASE-FX operation, the NetPHY-1LP device
receives a PECL data stream from the fiber optic trans-
ceiver and decodes that data stream.
The 100BASE-X block consists of the following sub-
blocks:
Transmit Process
The transmit process generates code-groups based on
the transmit control and data signals on the MII. This
process is also responsible for frame encapsulation
into a Physical Layer Stream, generating the collision
signal based on whether a carrier is received simulta-
neously during transmission and generating the Carrier
Sense CRS and Collision COL signals at the MII. The
transmit process is implemented in compliance with the
18
— Transmit Process
— Receive Process
— 4B/5B Encoder and Decoder
— Scrambler/Descrambler
— Link Monitor
— Far End Fault Generation and Detection &
— MLT-3 encoder/decoder with Adaptive
— Baseline Restoration
— Clock Recovery
NetPHY-1LP
Code-Group Generator
Equalization
Am79C874
TEST1/FXR+
TEST0/FXR-
TEST3/SDI+
FX_SEL
ANEGA
FXT+
FXT-
1 kΩ
183 Ω
1 kΩ
69 Ω
Figure 1. FXT± and FXR± Termination for 100BASE-FX
3.3 V
183 Ω
69 Ω
130 Ω
82.5 Ω
0.01 μF
0.1 μF
D A T A
Am79C874
3.3 V
0.1 μF
82.5 Ω
130 Ω
82.5 Ω 130 Ω 130 Ω
130 Ω
transmit state diagram as defined in Clause 24 of the
IEEE 802.3u specification.
The NetPHY-1LP device transmit function converts
synchronous 4-bit data nibbles from the MII to a 125-
Mbps differential serial data stream. The entire opera-
tion is synchronous to a 25-MHz clock and a 125-MHz
clock. Both clocks are generated by an on-chip PLL
clock synthesizer that is locked to an external 25-MHz
clock source.
In 100BASE-FX mode, the NetPHY-1LP device will by-
pass the scrambler. The output data is an NRZI PECL
signal. This PECL level signal will then drive the Fiber
transmitter.
Receive Process
The receive path includes a receiver with adaptive
equalization and DC restoration, MLT-3-to-NRZI con-
version, data and clock recovery at 125-MHz, NRZI-to-
NRZ conversion, Serial-to-Parallel conversion, de-
scrambling, and 5B to 4B decoding. The receiver circuit
starts with a DC bias for the differential RX± inputs, fol-
lows with a low-pass filter to filter out high-frequency
noise from the transmission channel media. An energy
detect circuit is also added to determine whether there
is any signal energy on the media. This is useful in the
power-saving mode. (See the description in Power
3.3 V
S H E E T
5 RD+
4 RD-
3 SD+
10 TD-
9 TD+
HFBR/HFCT-5903
3.3 V MT-RJ
22236G-3
22235K