AM79C874VC AMD (ADVANCED MICRO DEVICES), AM79C874VC Datasheet - Page 33

• Manufacturer Part Number: AM79C874VC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C874VC

• Lead Free Status / RoHS Status: Not Compliant

22235K
Reg
Reg
2
1
1
1
1
1
1
1
1
1
1
1
1
1
15:0
10:7
Bit
15
14
13
12
11
5
4
3
2
1
0
6
Name
OUI
Name
100BASE-T4
100BASE-TX Full
Duplex
100BASE-TX Half
Duplex
10BASE-T Full
Duplex
10BASE-T Half
Duplex
Reserved
Management
Frame Preamble
Suppression
Auto-Negotiation
Complete
Remote Fault
Auto-Negotiation
Ability
Link Status
Jabber Detect
Extended
Capability
Table 15. MII Management Status Register (Register 1)
Table 16. PHY Identifier 1 Register (Register 2)
Description
Composed of the 3rd through 18th bits of the Organizationally
Unique Identifier (OUI), respectively.
Description
1 = 100BASE-T4 able.
0 = Not 100BASE-T4 able.
1 = 100BASE-TX Full Duplex.
0 = No 100BASE-TX Full Duplex ability.
1 = 100BASE-TX Half Duplex.
0 = No TX half-duplex ability.
1 = 10BASE-T Full Duplex.
0 = No 10BASE-T Full Duplex ability.
1 = 10BASE-T Half Duplex.
0 = No 10BASE-T ability.
Ignore when read.
The device accepts management frames that do not have a
preamble after receiving a management frame with a 32-bit or
longer preamble.
1 = Auto-Negotiation process completed. Registers 4, 5, and 6
are valid after this bit is set.
0 = Auto-Negotiation process not completed.
1 = Remote fault condition detected.
0 = No remote fault.
This bit will remain set until it is read via the management
interface.
1 = Able to perform Auto-Negotiation function; value is
determined by ANEGA pin.
0 = Unable to perform Auto-Negotiation function.
1 = Link is established; however, if the NetPHY-1LP device link
fails, this bit will be cleared and remain cleared until Register 1
is read via management interface.
0 = link is down.
1 = Jabber condition detected.
0 = No Jabber condition detected.
1 = Extended register capable. This bit is tied permanently to
one.
D A T A
S H E E T
Am79C874
RO/LH
RO/LH
RO/LL
Read/
Write
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Read/
Write
RO
ANEGA pin
TECH[2:0]
TECH[2:0]
TECH[2:0]
TECH[2:0]
Default
set by
set by
set by
set by
set by
0022(H)
Default
pins
pins
pins
pins
0
0
0
0
0
0
1
1
33