AM79C874VC AMD (ADVANCED MICRO DEVICES), AM79C874VC Datasheet - Page 15

• Manufacturer Part Number: AM79C874VC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C874VC

• Lead Free Status / RoHS Status: Not Compliant

Note: If 7-Wire mode is chosen the polarity of the LED
should be reversed and the cathode of the LED should
be tied to ground.
LEDSPD[0]/LEDBTA/FX_SEL
100 Mbps Speed LED/Advanced LED/Fiber Select
When this pin is pulled low via a 1 kΩ resistor, on the
rising edge of reset, the device will be enabled for
100BASE-FX operation. When no pull-down resistor is
present, on the rising edge of reset, the device will be
enabled for 100BASE-TX or 10BASE-T operation.
When the standard LED configuration is enabled (see
LEDRX/LEDSEL pin description), this pin serves as the
100 Mbps speed LED. A logic low level indicates 100
Mbps operation. A logic high level indicates 10 Mbps
operation. Refer to Figure 5 in the LED Port Configura-
tion section to determine the correct polarity of the
LED.
When the advanced LED configuration is enabled, this
pin works in conjunction with LEDTX/LEDBTB (pin 47).
Refer to Table 7 and Figure 6 in the LED Port Configu-
ration section to determine the correct polarity of the bi-
directional LED.
LEDTX/LEDBTB
Transmit LED/Advanced LED
When the standard LED configuration is enabled (see
LEDRX/LEDSEL pin description), this pin serves as the
transmit LED. This pin toggles between high and low
when data is transmitted. Refer to Figure 5 in the LED
Port Configuration section to determine the correct po-
larity of the LED.
When the advanced LED configuration is enabled, this
pin works in conjunction with LEDSPD[0]/LEDBTA/
FX_SEL (pin 44). Refer to Table 7 and Figure 6 in the
LED Port Configuration section to determine the cor-
rect polarity of the bi-directional LED.
LEDSPD[1]/LEDTXA/CLK25EN
10 Mbps Speed LED/Advanced LED/25 MHz Clock
Enable
When this pin is pulled low via a 1 kΩ resistor, on the
rising edge of reset, the device will output a 25 MHz
clock on CLK25 (pin 6). When no pull-down resistor is
present, on the rising edge of reset, CLK25 is inactive.
When the standard LED configuration is enabled (see
LEDRX/LEDSEL pin description), this pin serves as the
10 Mbps speed LED. A logic low level indicates 10
Mbps operation. A logic high level indicates 100 Mbps
operation. Refer to Figure 5 in the LED Port Configura-
tion section to determine the correct polarity of the
LED.
When the advanced LED configuration is enabled, this
pin works in conjunction with LEDDPX/LEDTXB (pin
58). Refer to Table 8 and Figure 6 in the LED Port Con-
22235K
Input/Output, Pull-Up
Input/Output, Pull-Up
D A T A
Output
S H E E T
Am79C874
figuration section to determine the correct polarity of
the bi-directional LED.
LEDDPX/LEDTXB
Duplex LED/Advanced LED
When the standard LED configuration is enabled (see
LEDRX/LEDSEL description), this pin serves as the
duplex LED. A logic low level indicates full duplex op-
eration. A logic high level indicates half duplex opera-
tion. See Figure 5 in the LED Port Configuration
section to determine the correct polarity of the LED.
When the advanced LED configuration is enabled, this
pin works in conjunction with LEDSPD[1] LEDTXA/
CLK25EN (pin 57). Refer to Table 8 and Figure 6 in the
LED Port Configuration section to determine the cor-
rect polarity of the bi-directional LED.
Bias
IBREF
Reference Bias Resistor
This pin must be tied to an external 10.0 kΩ (1%) resis-
tor which should be connected to ground. The 1% re-
sistor provides the bandgap reference voltage.
Note: This signal trace should be short and not close
to other signals.
Power and Ground
PLLVCC, OVDD1, OVDD2, VDD1, VDD2, CRVVCC,
ADPVCC, EQVCC, REFVCC, TVCC1, TVCC2
Power Pins
These pins are 3.3 V power for sections of the
NetPHY-1LP device as follows:
PLLVCC is power for the PLL; OVDD1 and OVDD2 are
power for the I/O; VDD1 and VDD2 are power for the
digital logic; CRVVCC is power for clock recovery; AD-
PVCC and EQVCC are power for the equalizer;
REFVCC is power for the bandgap reference; and
TVCC1 and TVCC2 are power for the transmit driver.
PLLGND, OGND1, OGND2, DGND1, DGND2,
CRVGND, EQGND, REFGND, TGND1, TGND2
Ground Pins
These pins are ground for the power pins as follows:
PLLGND is ground for PLLVCC; OGND is ground for
OVDD; DGND is ground for VDD; CRVGND is ground
for CRVVCC and ADPVCC; EQGND is ground for
EQVCC; REFGND is ground for REFVCC; and TGND
is ground for TVCC.
Note: Bypass capacitors of 0.1 μF between the power
and ground pins are recommended. The four areas
where the capacitors must be very close to the pins
(within 3 mm) are the PLL (pins 10 and 11), Clock Re-
covery (pins 51 and 52), Equalizer (pins 60 and 65),
and Bandgap Reference (pins 71 and 73) areas. The
other bypass capacitors should be placed as close to
the pins as possible.
Analog
Output
Power
Power
15