AM79C874VC AMD (ADVANCED MICRO DEVICES), AM79C874VC Datasheet - Page 19

• Manufacturer Part Number: AM79C874VC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C874VC

• Lead Free Status / RoHS Status: Not Compliant

Savings Mechanisms section). All of the amplification
ratio and slicer thresholds are set by the on-chip band-
gap reference.
In 100BASE-FX mode, signal will be received through
a PECL receiver, and directly passed to the clock re-
covery for data/clock extraction. In FX mode, the
scrambler/descrambler cipher will be bypassed.
4B/5B Encoder/Decoder
The 100 Mbps process in the NetPHY-1LP device uses
the 4B/5B encoding scheme as defined in IEEE 802.3,
Section 24. This scheme converts between raw data on
the MII and encoded data on the media pins. The en-
coder converts raw data to the 4B/5B code. It also in-
serts the stream boundary delimiters (/J/K/ and /T/R/)
at the beginning and end of the data stream as appro-
priate. The decoder converts between encoded data
on the media pins and raw data on the MII. It also de-
tects the stream boundary delimiters to help determine
the start and end of packets. The code-group mapping
is defined in Table .
The 4B/5B encoding is bypassed when MII Register
21, bit 1 is set to “1”, or the PCSBP pin (pin 1) is
strapped high.
Scrambler/Descrambler
The 4B/5B encoded data has repetitive patterns which
result in peaks in the RF spectrum large enough to
keep the system from meeting the standards set by
regulatory agencies such as the FCC. The peaks in the
radiated signal are reduced significantly by scrambling
the transmitted signal. Scramblers add the output of a
random generator to the data signal. The resulting sig-
nal has fewer repetitive data patterns.
After reset, the scrambler seed in each port will be set
to the PHY address value to help improve the EMI per-
formance of the device.
The scrambled data stream is descrambled at the re-
ceiver by adding it to the output of another random gen-
erator. The receiver’s random generator uses the same
function as the transmitter’s random generator.
In 100BASE-TX mode, all 5-bit transmit data streams
are scrambled as defined by the TP-PMD Stream
22235K
D A T A
S H E E T
Am79C874
Cipher function in order to reduce radiated emissions
on the twisted pair cable. The scrambler encodes a
plain text NRZ bit stream using a key stream periodic
sequence of 2047 bits generated by the recursive
linear function:
The scrambler reduces peak emissions by randomly
spreading the signal energy over the transmit
frequency range, thus eliminating peaks at a single fre-
quency.
When MII Register 21, bit 2 is set to “1,” the data
scrambling function is disabled and the 5-bit data
stream is clocked directly to the device’s PMA sub-
layer.
Link Monitor
Signal levels are detected through a squelch detection
circuit. A signal detect (SD) circuit following the equal-
izer is asserted high whenever the peak detector
senses a post-equalized signal with a peak-to-ground
voltage level larger than 400 mV. This is approximately
40 percent of the normal signal voltage level. In addi-
tion, the energy level must be sustained longer than
2 ms in order for the signal detect to be asserted. It gets
de-asserted approximately 1 ms after the energy level
is consistently less than 300 mV from peak-to-ground.
The link signal is forced to low during a local loopback
operation (i.e., when MII Register 0, bit 14, Loopback is
asserted) and forced to high when a remote loopback
is taking place (i.e., when MII Register 21, bit 3,
EN_RPBK, is set).
In 100BASE-TX mode, when no signal or an invalid
signal is detected on the receive pair, the link monitor
will enter in the “link fail” state where only the scram-
bled idle code will be transmitted. When a valid signal
is detected for a minimum period of time, the link mon-
itor will then enter the link pass state when transmit and
receive functions are entered.
In 100BASE-FX mode, the external fiber-optic receiver
performs the signal energy detection function and com-
municates this information directly to the NetPHY-1LP
device through the SDI+ pin.
X[n] = X[n-11] + X[n-9] (modulo 2)
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