AM79C874VC AMD (ADVANCED MICRO DEVICES), AM79C874VC Datasheet - Page 32

• Manufacturer Part Number: AM79C874VC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C874VC

• Lead Free Status / RoHS Status: Not Compliant

32
Reg
0
0
0
0
0
0
0
0
0
0
6:0
Bit
15
14
13
12
10
11
9
8
7
Name
Reset
Loopback
Speed Select
Auto-Neg
Enable
Power Down
Isolate
Restart Auto-
Negotiation
Duplex Mode
Collision Test
Reserved
Table 14. MII Management Control Register (Register 0)
Description
1 = PHY reset.
0 = Normal operation.
This bit is self-clearing. This Reset will require a minimum of 1 ms,
or is complete when the register clears.
1 = Enable loopback mode. This will loopback TXD to RXD, thus it
will ignore all the activity on the cable media. During loopback, a
10-Mbps link is sent to the link partner (Register 21, bit 14 is forced.)
0 = Disable Loopback mode. Normal operation.
1 = 100 Mbps, 0 = 10 Mbps. This bit will be ignored if Auto
Negotiation is enabled (0.12 = 1).
Refer to Table 3 to determine when this bit can be changed.
1 = Enable auto-negotiate process (overrides 0.13 and 0.8).
0 = Disable auto-negotiate process. Mode selection is controlled via
bit 0.8, 0.13 or through TECH[2:0] pins.
Refer to Table 3 to determine when this bit can be changed.
1 = Power down. The NetPHY-1LP device will shut off all blocks
except for MDIO/MDC interface. Setting PWRDN pin to high will
achieve the same result.
0 = Normal operation.
1 = Electrically isolate the PHY from MII. However, PHY is still able
to respond to MDC/MDIO. The default value of this bit depends on
ISODEF pin, i.e., ISODEF=1, ISO bit will set to 1, & ISODEF=0, ISO
bit will set to 0.
0 = Normal operation.
1 = Restart Auto-Negotiation process.
0 = Normal operation.
1 = Full duplex, 0 = Half duplex.
Refer to Table 3 to determine when this bit can be changed.
1 = Enable collision test, which issues the COL signal in response
to the assertion of TX_EN signal. Collision test is disabled if PCSBP
pin is high. Collision test is enabled regardless of the duplex mode.
0 = disable COL test.
Write as 0, ignore when read.
D A T A
Am79C874
S H E E T
RW/SC
RW/SC
Read/
Write
RW
RW
RW
RW
RW
RW
RW
RW
TECH[2:0]
TECH[2:0]
ISODEF
Default
ANEGA
Set by
Set by
Set by
Set by
22235K
pins
pins
pin
pin
0
0
0
0
0
0