AM79C874VC AMD (ADVANCED MICRO DEVICES), AM79C874VC Datasheet - Page 22

• Manufacturer Part Number: AM79C874VC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C874VC

• Lead Free Status / RoHS Status: Not Compliant

Clock/Data Recovery
The equalized MLT-3 signal passes through a slicer cir-
cuit which then converts it to NRZI format. The Net-
PHY-1LP device uses an analog phase-locked loop
(APLL) to extract clock information from the incoming
NRZI data. The extracted clock is used to re-time the
data stream and set the data boundaries. The transmit
clock is locked to the 25-MHz clock input, while the re-
ceive clock is locked to the incoming data streams.
When initial lock is achieved, the APLL switches to lock
to the data stream, extracts a 125 MHz clock from it
and use that for bit framing to recover data. The recov-
ered 125 MHz clock is also used to generate the 25
MHz RX_CLK. The APLL requires no external compo-
nents for its operation and has high noise immunity and
low jitter. It provides fast phase align (lock) to data in
one transition and its data/clock acquisition time after
power-on is less than 60 transitions.
The APLL can maintain lock on run-lengths of up to 60
data bits in the absence of signal transitions. When no
valid data is present, i.e., when the SD is de-asserted,
the APLL switches back to lock with TX_CLK, thus pro-
viding a continuously running RX_CLK.
22
RX+
TX+
RX-
TX-
(Note 1)
(Note 2)
2. 49.9 Ω is normal, but 54.9 Ω can be used for extended cable length operation.
Notes:
1. 49.9 Ω if a 1:1 isolation transformer is used or 78.1 Ω if a 1.25:1 isolation transformer is used.
(Note 1)
V
(Note 2)
Figure 3. TX± and RX± Termination for 100BASE-TX and 10BASE-T
DD
0.1 μF
0.1 μF
0.1 μF
Transformer with
common-mode
1:1 or 1.25:1
Isolation
chokes
D A T A
Am79C874
1:1
The recovered data is converted from NRZI-to-NRZ
and then to a 5-bit parallel format. The 5-bit parallel
data is not necessarily aligned to 4B/5B code-group’s
symbol boundary. The data is presented to PCS at re-
ceive data register output, gated by the 25-MHz
RX_CLK.
PLL Clock Synthesizer
The NetPHY-1LP device includes an on-chip PLL clock
synthesizer that generates a 125 MHz and a 25 MHz
clock for the 100BASE-TX or a 100 MHz and 20 MHz
clock for the 10BASE-T and Auto-Negotiation opera-
tions. Only one external 25 MHz crystal or a signal
source is required as a reference clock.
After power-on or reset, the PLL clock synthesizer is
defaulted to generating the 20 MHz clock output and
will stay active until the 100BASE-X operation mode is
selected.
Clock and Crystal Inputs
A 25 MHz crystal can be used for XTL± inputs to the
NetPHY-1LP. The crystal should be parallel resonant
and have a frequency stability of ±100 ppm and a fre-
quency tolerance ±50 ppm. Recommended parts are
75Ω
S H E E T
75 Ω
75Ω
(chassis ground)
75 Ω
470 pF, 2 kV
(8)
(7)
TX+ (1)
(5)
(4)
TX- (2)
RX+ (3)
RX- (6)
Connector
RJ45
22236G-5
22235K