AM79C874VC AMD (ADVANCED MICRO DEVICES), AM79C874VC Datasheet - Page 30

• Manufacturer Part Number: AM79C874VC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C874VC

• Lead Free Status / RoHS Status: Not Compliant

PHY CONTROL AND MANAGEMENT
BLOCK (PCM BLOCK)
Register Administration for 100BASE-X
PHY Device
The management interface specified in Clause 22 of
the IEEE 802.3u standard provides for a simple two
wire, serial interface to connect a management entity
and a managed PHY for the purpose of controlling the
PHY and gathering status information. The two lines
are Management Data Input/Output (MDIO), and Man-
The PHYAD field, which is five bits wide, allows 32
unique PHY addresses. The managed PHY layer de-
vice that is connected to a station management entity
via the MII interface has to respond to transactions
addressed to the PHY address. A station management
30
WRITE
READ
WRITE
READ
MDIO
(STA)
MDC
(PHY)
MDIO
(STA)
MDIO
MDC
z
Idle
z
PRE
1.1
1.1
z
Idle
z
PRE
0
1.1
1.1
Start
0
Start
1
1
Opcode
(Write)
0
ST
01
01
Opcode
(Read)
1
1
ST
0
Figure 7. PHY Management Read and Write Operations
01
01
1
1
PHY Address
OP
10
01
16h, Port 2
0
Table 10. Clause 22 Management Frame Format
Table 11. PHY Address Setting Frame Structure
PHY Address
16h, Port 2
0
1
1
OP
10
01
1
1
PHYAD
0
00000
00000
0
0
Register Address
MII Control, 0h
0
Register Address
0
MII Status, 1h
0
PHYAD
AAAAA
AAAAA
0
0
0
D A T A
0
Am79C874
REGADD
RRRRR
RRRRR
0
1
z
z
Write Operation
Read Operation
1
TA
z
TA
0
0
agement Data Clock (MDC). A station management
entity which is attached to multiple PHY entities must
have prior knowledge of the appropriate PHY address
for each PHY entity.
Description of the Methodology
The management interface physically transports man-
agement information across the MII. The information is
encapsulated in a frame format as specified in Clause
22 of IEEE 802.3u draft standard and is shown in
Table .
entity attached to multiple PHYs, such as in a managed
802.3 Repeater or Ethernet switch, is required to have
prior knowledge of the appropriate PHY address. See
Table and Figure 7.
0
REGADD
0
RRRRR
RRRRR
S H E E T
1
1
TA
Z0
1
10
1
0
0
0
0
0
0
0
XXXXXXXXXPPAAAAA
XXXXXXXXXPPAAAAA
Register Data
0
TA
Z0
10
Register Data
1
0
0
0
DATA
0
1
0
D...........D
D...........D
0
0
DATA
0
0
0
0
0
0
0
0
1
Idle
z
z
22236G-9
z
z
Idle
IDLE
22235K
IDLE
Z
Z
Z
Z