PIC32MX575F256LT-80I/PT Microchip Technology, PIC32MX575F256LT-80I/PT Datasheet - Page 16

• Manufacturer Part Number: PIC32MX575F256LT-80I/PT
• Description: 256KB Flash, 64KB RAM, 80 MHz, USB, 1xCAN, 8 DMA 100 TQFP 12x12x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX575F256LT-80I/PT

• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC32MX
7.0
For 2-wire programming methods, the target device
must be placed in a special programming mode before
executing further steps.
The following steps are required to enter Programming
mode:
1.
2.
3.
Please refer to 20.0 “AC/DC Characteristics and
Timing Requirements” for timing requirements.
FIGURE 7-1:
DS61145G-page 16
Note:
The MCLR pin is briefly driven high, then low.
A 32-bit key sequence is clocked into PGDx.
MCLR is then driven high within a specified
period of time and held.
MCLR
V
PGDx
PGCx
DD
ENTERING PROGRAMMING
MODE
If a 4-wire programming method is used, it
is not necessary to enter the Programming
mode.
P6
ENTERING ENHANCED ICSP™ MODE
P14
P16
P20
V
b31
0
IH
b30
1
Program/Verify Entry Code = 0x4D434850
b29
0
P2B
b28
0
P2A
b27
1
The programming voltage applied to MCLR is V
which is essentially V
no minimum time requirement for holding at V
V
before presenting the key sequence on PGDx.
The key sequence is a specific 32-bit pattern: ‘0100
1101 0100 0011 0100 1000 0101 0000’ (the
acronym ‘MCHP’, in ASCII). The device will enter
Program/Verify mode only if the key sequence is valid.
The MSb of the Most Significant nibble must be shifted
in first.
Once the key sequence is complete, V
applied to MCLR and held at that level for as long as
Programming mode is to be maintained. An interval of
at least time P17 and P7 must elapse before presenting
data on PGDx. Signals appearing on PGDx before P7
has elapsed will not be interpreted as valid.
Upon successful entry, the program memory can be
accessed and programmed in serial fashion. While in
Programming mode, all unused I/Os are placed in the
high-impedance state.
IH
is removed, an interval of at least P16 must elapse
...
0
b3
0
b2
DD
0
b1
V
, in PIC32MX devices. There is
© 2010 Microchip Technology Inc.
IH
0
b0
P17
P7
IH
must be
IH
. After
IH
,