PIC32MX575F256LT-80I/PT Microchip Technology, PIC32MX575F256LT-80I/PT Datasheet - Page 6

• Manufacturer Part Number: PIC32MX575F256LT-80I/PT
• Description: 256KB Flash, 64KB RAM, 80 MHz, USB, 1xCAN, 8 DMA 100 TQFP 12x12x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX575F256LT-80I/PT

• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC32MX
5.0
Programming is accomplished via the EJTAG module
in the CPU core. EJTAG is connected to either the full
set of JTAG pins, or a reduced 2-wire to 4-wire EJTAG
interface. In both modes, programming of the PIC32MX
Flash memory is accomplished through the ETAP
controller. The TAP Controller uses the TMS pin to
determine if Instruction or Data registers should be
accessed in the shift path between TDI and TDO (see
Figure 5-1).
FIGURE 5-1:
The basic concept of EJTAG that is used for program-
ming is the use of a special memory area called
DMSEG (0xFF200000 to 0xFF2FFFFF), which is only
available when the processor is running in Debug
mode. All instructions are serially shifted into an inter-
nal buffer, then loaded into the Instruction register and
executed by the CPU. Instructions are fed through the
ETAP state machine in 32-bit groups.
FIGURE 5-2:
DS61145G-page 6
TMS
TCK
TDO
TDI
TDO
TMS
TCK
TDI
PGD
PGC
OR
EJTAG vs. ICSP
Tap Controller
Instruction, Data and Control
MTAP
ETAP
4-wire
2-wire
TAP CONTROLLER
BASIC PIC32MX
PROGRAMMING BLOCK
to
Registers
Flash
Cntlr
Flash
Mem
CPU
Common
MCLR
V
V
DD
SS
• ETAP
• MTAP
• 2-Wire to 4-Wire
• CPU
• Flash Controller
• Flash Memory
- Serially feeds instructions and data into CPU.
- In addition to the EJTAG TAP (ETAP) control-
- The programmer sends commands by
- The probe does not need to issue an
- Converts 2-wire ICSP interface to 4-wire
- The CPU executes instructions at 8 MHz via
- The Flash Controller controls erasing and
- The PIC32MX device Flash memory is
- The last four implemented program memory
ler, the PIC32MX device uses a second
proprietary TAP controller for additional oper-
ations. The Microchip TAP (MTAP) controller
supports two instructions relevant to pro-
gramming: MTAP_COMMAND and TAP switch
Instructions. See Table 19-1 for a complete
list of Instructions. The MTAP_COMMAND
instruction provides a mechanism for a JTAG
probe to send commands to the device via its
Data register.
shifting in the MTAP_COMMAND instruction via
the SendCommand pseudo operation, and
then sending MTAP_COMMAND DR
commands via XferData pseudo operation
(see Table 19-2 for specific commands).
MTAP_COMMAND instruction for every
command shifted into the Data register.
JTAG.
the internal oscillator.
programming of the Flash memory on the
device.
divided into two logical Flash partitions con-
sisting of the Boot Flash Memory (BFM) and
Program Flash Memory (PFM). The Boot
Flash Memory map extends from
0x1FC00000 to 0x1FC02FFF, and the
Program Flash Memory map extends from
0x1D000000 to 0x1D07FFFF. Code storage
begins with the BFM and supports up to
12 Kbytes. It continues with the PFM, which
supports up to 512 Kbytes. Table 5-1 shows
the program memory size of each device
variant. Each erase block, or page, contains
1K instructions (4 Kbytes), and each program
block, or row, contains 128 instructions (512
bytes).
locations in BFM are reserved for the device
Configuration registers.
© 2010 Microchip Technology Inc.