PIC32MX575F256LT-80I/PT Microchip Technology, PIC32MX575F256LT-80I/PT Datasheet - Page 55

• Manufacturer Part Number: PIC32MX575F256LT-80I/PT
• Description: 256KB Flash, 64KB RAM, 80 MHz, USB, 1xCAN, 8 DMA 100 TQFP 12x12x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX575F256LT-80I/PT

• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.0
TABLE 19-1:
19.1
19.1.1
MTAP_COMMAND selects the MCHP Command Shift
register. See Table 19-2 for available commands.
19.1.1.1
MCHP_STATUS returns the 8-bit Status value of the
Microchip TAP controller. Table 19-3 shows the format
of the Status value returned.
19.1.1.2
MCHP_ASERT_RST performs a persistent device
Reset. It is similar to asserting and holding MCLR with
the exception that test modes are not detected. Its
associated Status bit is DEVRST.
19.1.1.3
MCHP_DE_ASERT_RST removes the persistent device
Reset. It is similar to de-asserting MCLR. Its associated
Status bit is DEVRST.
19.1.1.4
MCHP_ERASE performs a Chip Erase. The CHIP_
ERASE command sets an internal bit that requests the
Flash Controller to perform the erase. Once the control-
ler becomes busy, as indicated by FCBUSY (Status
bit), the internal bit is cleared.
TABLE 19-2:
© 2010 Microchip Technology Inc.
MTAP_COMMAND
MTAP_SW_MTAP
MTAP_SW_ETAP
MTAP_IDCODE
MCHP_STATUS
MCHP_ASERT_RST
MCHP_DE_ASERT_RST
MCHP_ERASE
MCHP_FLASH_ENABLE
MCHP_FLASH_DISABLE
Command
TAP CONTROLLERS
Microchip TAP Controllers (MTAP)
Command
MTAP_COMMAND INSTRUCTION
MCHP_STATUS INSTRUCTION
MCHP_ASERT_RST INSTRUCTION
MCHP_DE_ASERT_RST
INSTRUCTION
MCHP_ERASE INSTRUCTION
MCHP TAP INSTRUCTIONS
MTAP_COMMAND DR COMMANDS
Value
5’h07
5’h04
5’h05
5’h01
Value
8’hD1
8’hD0
8’hFC
8’hFE
8’hFD
8’h00
TDI and TDO connected to MCHP Command Shift register (See Table 19-2).
Switch TAP controller to MCHP TAP controller.
Switch TAP controller to EJTAG TAP controller.
Select Chip Identification Data register.
NOP and return Status.
Requests the reset controller to assert device Reset.
Removes the request for device Reset, which causes the reset
controller to de-assert device Reset if there is no other source
requesting Reset (i.e., MCLR).
Cause the Flash controller to perform a Chip Erase.
Enables fetches and loads to the Flash (from the processor).
Disables fetches and loads to the Flash (from the processor).
19.1.1.5
MCHP_FLASH_ENABLE sets the FAEN bit, which con-
trols processor accesses to the Flash memory. The
FAEN bit’s state is returned in the field of the same
name. This command has no effect if CPS = 0. This
command requires a NOP to complete.
19.1.1.6
MCHP_FLASH_DISABLE clears the FAEN bit which
controls processor accesses to the Flash memory. The
FAEN bit’s state is returned in the field of the same
name. This command has no effect if CPS = 0. This
command requires a NOP to complete.
19.1.2
MTAP_SW_MTAP switches the TAP instruction set to the
MCHP TAP instruction set.
19.1.3
MTAP_SW_ETAP effectively switches the TAP instruc-
tion set to the EJTAG TAP instruction set. It does this
by holding the EJTAG TAP controller in the Run Test/
Idle state until a MTAP_SW_ETAP instruction is decoded
by the MCHP TAP controller.
Description
MTAP_SW_MTAP INSTRUCTION
MTAP_SW_ETAP INSTRUCTION
Description
MCHP_FLASH_ENABLE
INSTRUCTION
MCHP_FLASH_DISABLE
INSTRUCTION
PIC32MX
DS61145G-page 55