PIC32MX575F256LT-80I/PT Microchip Technology, PIC32MX575F256LT-80I/PT Datasheet - Page 20

256KB Flash, 64KB RAM, 80 MHz, USB, 1xCAN, 8 DMA 100 TQFP 12x12x1mm T/R

PIC32MX575F256LT-80I/PT

Manufacturer Part Number
PIC32MX575F256LT-80I/PT
Description
256KB Flash, 64KB RAM, 80 MHz, USB, 1xCAN, 8 DMA 100 TQFP 12x12x1mm T/R
Manufacturer
Microchip Technology
Series
PIC® 32MXr

Specifications of PIC32MX575F256LT-80I/PT

Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC32MX575F256LT-80I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC32MX
11.0
The PE resides in RAM memory and is executed by the
CPU to program the device. The PE provides the
mechanism for the programmer to program and verify
PIC32MX devices using a simple command set and
communication protocol. There are several basic
functions provided by the PE:
• Read Memory
• Erase Memory
• Program Memory
• Blank Check
• Read Executive Firmware Revision
• Get the cyclic redundancy check (CRC) of Flash
The PE performs the low-level tasks required for
programming and verifying a device. This allows the
programmer to program the device by issuing the
appropriate commands and data. A detailed descrip-
tion for each command is provided in 16.2 “The PE
Command Set”.
The PE uses the device’s data RAM for variable stor-
age and program execution. After the PE has run, no
assumptions should be made about the contents of
data RAM.
After the PE is loaded into the data RAM, the PIC32MX
family can be programmed using the command set
shown in Table 16-1.
FIGURE 11-1:
Loading the PE in the memory is a two step process:
1.
2.
DS61145G-page 20
memory locations
Load the PE loader in the data RAM. (The PE
loader loads the PE binary file in the proper loca-
tion of the data RAM, and when done, jumps to
the programming exec and starts executing it.)
Feed the PE binary to the PE loader.
DOWNLOADING THE
PROGRAMMING EXECUTIVE
(PE)
Write the PE Loader to RAM
Load the PE
DOWNLOADING THE PE
Table 11-1 lists the steps that are required to download
the PE.
TABLE 11-1:
Step 1: Initialize BMXCON to 0x1f0040. The
lui
ori
lui
ori
sw
XferInstruction
XferInstruction
XferInstruction
XferInstruction
XferInstruction
Step 2: Initialize BMXDKPBA to 0x800. The
li
sw
XferInstruction
XferInstruction
Step 3: Initialize BMXDUDBA and BMXDUPBA to the
value of BMXDRMSZ. The instruction sequence exe-
cuted by the PIC32MX core is as follows:
lw
sw
sw
XferInstruction
XferInstruction
XferInstruction
Step 4: Set up PIC32MX RAM address for PE. The
lui
ori
XferInstruction
XferInstruction
Operation
a0,0xbf88
a0,a0,0x2000 /* address of BMXCON */
a1,0x1f
a1,a1,0x40
a1,0(a0)
a1,0x800
a1,16(a0)
a1,64(a0)
a1,32(a0)
a1,48(a0)
a0,0xa000
a0,a0,0x800
instruction sequence executed by the
PIC32MX core is as follows:
instruction sequence executed by the
PIC32MX core is as follows:
instruction sequence executed by the
PIC32MX core is as follows:
DOWNLOAD THE PE
0x3c04bf88
0x34842000
0x3c05001f
0x34a50040
0xac850000
0x34050800
0xac850010
0x8C850040
0xac850020
0xac850030
0x3c04a000
0x34840800
/* $a1 has 0x1f0040 */
/* BMXCON initialized */
/* load BMXDMSZ */
© 2010 Microchip Technology Inc.
Operand

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