PIC32MX575F256LT-80I/PT Microchip Technology, PIC32MX575F256LT-80I/PT Datasheet - Page 9

• Manufacturer Part Number: PIC32MX575F256LT-80I/PT
• Description: 256KB Flash, 64KB RAM, 80 MHz, USB, 1xCAN, 8 DMA 100 TQFP 12x12x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX575F256LT-80I/PT

• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.2
In ICSP mode, the 2-wire ICSP signals are time
multiplexed into the 2-wire to 4-wire block. The 2-wire
to 4-wire block then converts the signals to look like a
4-wire JTAG port to the TAP controller.
There are two possible modes of operation:
• 4-Phase ICSP
• 2-Phase ICSP
5.2.1
In 4-Phase ICSP mode, the TDI, TDO and TMS device
pins are multiplexed onto PGD in 4 clocks (see
Figure 5-4). The Least Significant bit (LSb) is shifted
first; and TDI and TMS are sampled on the falling edge
FIGURE 5-4:
FIGURE 5-5:
© 2010 Microchip Technology Inc.
TMS
TMS
TCK
TDO
TCK
TDO
TDI
TDI
2-Wire ICSP Details
4-PHASE ICSP
‘1’
‘1’
PGC
PGD
2-WIRE, 4-PHASE
2-WIRE, 2-PHASE
‘1’
‘1’
pTDO = 1
‘0’
‘0’
PGD
PGC
‘0’
‘0’
TDI = IR0
TDI = IR0
IR0
IR0
1
1
TMS = 0
TMS = 0
of PGC, while TDO is driven on the falling edge of PGC.
4-Phase mode is used for both read and write data
transfers.
5.2.2
In 2-Phase ICSP mode, the TMS and TDI device pins
are multiplexed into PGD in 2 clocks (see Figure 5-5).
The LSb is shifted first; and TDI and TMS are sampled
on the falling edge of PGC. There is no TDO output pro-
vided in this mode. The 2-Phase ICSP mode was
designed to accelerate 2-wire, write-only transactions.
Note:
The packet is not actually executed until the
first clock of the next packet.
To enter 2-Wire, 2-Phase ICSP mode, the
TDOEN bit (DDPCON<0>) must be set to
‘0’.
nTDO = 0
2-PHASE ICSP
‘1’
‘1’
IR4
IR4
X
X
‘1’
‘1’
PIC32MX
‘0’
‘0’
DS61145G-page 9