PIC32MX575F256LT-80I/PT Microchip Technology, PIC32MX575F256LT-80I/PT Datasheet - Page 37

• Manufacturer Part Number: PIC32MX575F256LT-80I/PT
• Description: 256KB Flash, 64KB RAM, 80 MHz, USB, 1xCAN, 8 DMA 100 TQFP 12x12x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX575F256LT-80I/PT

• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.0
17.1
The checksum is calculated as the 32-bit summation of
all bytes (8-bit quantities) in program Flash, boot Flash
(except device Configuration Words), the Device ID
register with applicable mask, and the device Configu-
ration Words with applicable masks. Next, the 2’s
complement of the summation is calculated. This final
32-bit number is presented as the checksum.
REGISTER 17-1:
© 2010 Microchip Technology Inc.
bit 31
bit 23
bit 15
bit 7
Legend:
R = readable bit
U = unimplemented bit, read as ‘0’
PWP15
R/P-1
r-0
r-1
r-1
—
—
—
CHECKSUM
Theory
PWP14
R/P-1
r-1
r-1
r-1
—
—
—
DEVCFG0 REGISTER OF PIC32MX360F512L
W = writable bit
PWP13
R/P-1
r-1
r-1
r-1
—
—
—
PWP12
R/P-1
R/P-1
CP
r-1
r-1
—
—
P = programmable bit
-n = bit value at POR: (‘0’, ‘1’, x = unknown)
ICESEL
17.2
The mask value of a device Configuration is calculated
by setting all the unimplemented bits to ‘0’ and all the
implemented bits to ‘1’.
For example, Register 17-1 shows the DEVCFG0 reg-
ister of the PIC32MX360F512L device. The mask value
for this register is:
Table 17-1 lists the mask values of the four device Con-
figuration registers and Device ID registers to be used
in the checksum calculations.
For quick reference, Table 17-2 shows the addresses
of DEVCFG and DEVID registers for currently
supported devices.
PWP19
R/P-1
R/P-1
r-1
r-1
—
—
mask_value_devcfg0 = 0x110FF00B
Mask Values
PWP18
R/P-1
r-1
r-1
r-1
—
—
—
r = reserved bit
PWP17
R/P-1
R/P-1
PIC32MX
r-1
r-1
—
—
DEBUG<1:0>
DS61145G-page 37
PWP16
R/P-1
R/P-1
R/P-1
BWP
r-1
—
bit 24
bit 16
bit 8
bit 0