PIC32MX575F256LT-80I/PT Microchip Technology, PIC32MX575F256LT-80I/PT Datasheet - Page 57

• Manufacturer Part Number: PIC32MX575F256LT-80I/PT
• Description: 256KB Flash, 64KB RAM, 80 MHz, USB, 1xCAN, 8 DMA 100 TQFP 12x12x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX575F256LT-80I/PT

• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.2
19.2.1
ETAP_ADDRESS selects the Address register. The
read-only Address register provides the address for a
processor access. The value read in the register is
valid if a processor access is pending, otherwise the
value is undefined.
The two or three Least Significant Bytes (LSBs) of the
register are used with the Psz field from the EJTAG
Control register to indicate the size and data position of
the pending processor access transfer. These bits are
not taken directly from the address referenced by the
load/store.
19.2.2
ETAP_DATA selects the Data register. The read/write
Data register is used for opcode and data transfers dur-
ing processor accesses. The value read in the Data
register is valid only if a processor access for a write is
pending, in which case the Data register holds the store
value. The value written to the Data register is only
used if a processor access for a pending read is fin-
ished afterwards; in which case, the data value written
is the value for the fetch or load. This behavior implies
that the Data register is not a memory location where a
previously written value can be read afterwards.
19.2.3
ETAP_CONTROL selects the Control register. The
EJTAG Control register (ECR) handles processor Reset
and soft Reset indication, Debug mode indication,
access start, finish and size, and read/write indication.
The ECR also provides the following features:
• Controls debug vector location and indication of
• Allows a debug interrupt request
• Indicates processor Low-Power mode
• Allows implementation-dependent processor and
© 2010 Microchip Technology Inc.
serviced processor accesses
peripheral Resets
EJTAG TAP Controller
ETAP_ADDRESS COMMAND
ETAP_DATA COMMAND
ETAP_CONTROL COMMAND
The EJTAG Control register is not updated/written in
the Update-DR state unless the Reset occurred; that is
R
the same time. This condition ensures proper handling
of processor accesses after a Reset.
Reset of the processor can be indicated through the
R
after it is removed in the processor clock domain in
order to allow for proper synchronization between the
two clock domains.
Bits that are R/W in the register return their written
value on a subsequent read, unless other behavior is
defined.
Internal synchronization ensures that a written value is
updated for reading immediately afterwards, even
when the TAP controller takes the shortest path from
the Update-DR to Capture-DR state.
19.2.4
The Reset value of the EjtagBrk, ProbTrap and ProbEn
bits follows the setting of the internal EJTAGBOOT
indication.
If the EJTAGBOOT instruction has been given, and the
internal EJTAGBOOT indication is active, then the
Reset value of the three bits is set (1), otherwise the
Reset value is clear (0).
The results of setting these bits are:
• Setting the EjtagBrk causes a Debug interrupt
• The debug handler is executed from the EJTAG
• Service of the processor access is indicated
Therefore, it is possible to execute the debug handler
right after a processor Reset from the EJTAGBOOT
instruction, without executing any instructions from the
normal Reset handler.
OCC
OCC
exception to be requested right after the
processor Reset from the EJTAGBOOT instruction
memory because ProbTrap is set to indicate
debug vector in EJTAG memory at 0x FF20 0200
because ProbEn is set
(bit 31) is either already ‘0’ or is written to ‘0’ at
bit in the TCK domain a number of TCK cycles
ETAP_EJTAGBOOT COMMAND
PIC32MX
DS61145G-page 57