LSI53CF92A LSI, LSI53CF92A Datasheet - Page 106

• Manufacturer Part Number: LSI53CF92A
• Manufacturer: LSI

Specifications of LSI53CF92A

• Lead Free Status / RoHS Status: Not Compliant

5.4.1 Transfer Information
5-14
Table 5.11
Table 5.11
This command can send or receive any Information phase bytes, but is
most often used for data transfer.
Command Set
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
Non-DMA
0x10
0x11
0x12
0x18
0x1A
0x1B
0x1E
Transfer is complete. Successful completion generates a Bus Service
interrupt. For DMA Transfer Information, the transfer is complete
when the transfer counter decrements to zero, the FIFO is empty and
the target asserts REQ/ for the next byte. For non-DMA Transfer
Information in which the FSC is sending bytes to the SCSI bus, the
transfer is complete when the FIFO empties and the target asserts
REQ/ for the next byte. For non-DMA Transfer Information in which
the FSC is receiving bytes from the SCSI bus, transfer is complete
after one byte is received and the target asserts REQ/ for the next
byte. Thus non-DMA Transfer Information commands generate an
interrupt for every byte received.
Note:
lists the Initiator commands.
Initiator Commands
For synchronous transfer, DMA must be used. The FSC
continues to transfer information until one of the following
terminating events occurs:
DMA
0x90
0x91
–
0x98
–
–
–
Mnemonic
Transfer Information
Initiator Command
Complete Sequence
Message Accepted
Transfer Pad
Set ATN
Reset ATN
Set ATN Immediate