LSI53CF92A LSI, LSI53CF92A Datasheet - Page 138

• Manufacturer Part Number: LSI53CF92A
• Manufacturer: LSI

Specifications of LSI53CF92A

• Lead Free Status / RoHS Status: Not Compliant

Table 6.17
1. Assertion pending. If the FIFO is empty during DMA read, or full during DMA write, then assertion
2. Single DMA transfer only.
3. DACK/ is used for DMA reads and writes. For DMA reads, DACK/ must toggle, and is assumed to
4. Multiple DMA transfers only.
5. Either DACK/ or DBWR/ may toggle during a burst write. Timings are shown for DBWR/ toggling;
6. DBWR/ LOW may precede DACK/ LOW.
6-22
Symbol
is not pending.
be coincident with an external read signal.
however, DACK/ and DBWR/ may be interchanged in
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
Parameter
DACK/ HIGH to DREQ HIGH
DACK/ LOW to DREQ LOW
DACK/ pulse width
DACK/ HIGH to DACK/ LOW
DACK/ LOW to data valid
DACK/ HIGH to data bus disable
DACK/ LOW to DACK/ LOW
DACK/ HIGH to DACK/ HIGH
DACK/ HIGH to DREQ LOW
DBWR/ LOW to DREQ LOW
DBWR/ pulse width
DBWR/ HIGH to DBWR/ LOW
DBWR/ LOW to DBWR/ LOW
DBWR/ HIGH to DBWR/ HIGH
DBWR/ HIGH to DREQ LOW
DACK/ LOW to DBWR/ LOW
Data setup to DBWR/ HIGH
Data hold from DBWR/ HIGH
Burst Mode DMA Interface (Nonmultiplexed Mode)
Table 6.17
Electrical Specifications
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
lists the Burst Mode DMA Interface, Nonmultiplexed Mode.
t
t
t
t
CP
CP
3 t
3 t
CP
CP
3 t
3 t
Min
30
15
–
–
–
–
–
–
0
4
Figure 6.20
CP
CP
CP
CP
+5
+5
+5
+5
2 t
2 t
CP
CP
and
Max
+ t
+ t
30
30
30
30
–
–
–
–
–
–
–
–
–
–
–
–
CL
CL
Table
+30
+30
6.17.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
2, 5
4, 5
5, 6
–
–
–
1
2
3
3
3
4
5
5
5
5
5
5