LSI53CF92A LSI, LSI53CF92A Datasheet - Page 40

• Manufacturer Part Number: LSI53CF92A
• Manufacturer: LSI

Specifications of LSI53CF92A

• Lead Free Status / RoHS Status: Not Compliant

2.8.2.3 Response to SCAM Selection
2-20
Step 5. Assert BSY/ using the
Step 6. Wait two de-skew delays.
Step 7. Assert SEL/ and I/O while maintaining BSY/ asserted. At this
Step 8. Assert DB6 and DB7 by first writing them in the
Step 9. Wait two de-skew delays.
Step 10. Release SEL/ and wait until SEL/ has been deasserted, using
Step 11. Release DB6 and examine the SCSI bus signals. If C/D is not
When response to SCAM selection is enabled (ENSS bit set in the
SCSI Control (SCONTROL)
SCAM selection attempts (SEL/ and MSG/ asserted when BSY/ released).
Upon detection of a SCAM selection, the FSC responds by asserting SEL/
and MSG/, and then interrupting the processor. A SCAM selection interrupt
is indicated when both bits 1 and 0 of the
mutually exclusive events). Following a SCAM selection interrupt, software
must enter the low-level programming mode and participate in the SCAM
protocol. The following minimal steps must be taken by software in
preparation for and response to the SCAM selection interrupt:
Step 1. In the
Step 2. Wait for SCAM Selection Interrupt.
Step 3. In the
Step 4. In the
Step 5. Release MSG/.
Functional Description
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
time, if the device is a SCAM master, C/D should also
be asserted.
Data Latch (SODL)
bit 2 of the
wired-OR glitch filtering in software.
asserted, then there are no SCAM master devices participating,
and the slave devices release all signals. If C/D is asserted,
wait for DB6 to be released by all devices, using wired-OR
glitch filtering, then assert SEL/. This completes initiation of the
SCAM selection protocol.
Low Level (bit 0).
SCSI Control (SCONTROL)
SCSI Output Control Latch (SOCL)
SCSI Control (SCONTROL)
SCSI Control (SCONTROL)
register), the FSC monitors the SCSI bus for
register, then enabling their drivers with
SCSI Output Data Latch (SODL)
Interrupt
set the ENSS (bit 3) and
register reset ENSS (bit 3).
register are set (normally
register.
set MSG (bit 2).
SCSI Output
register.