LSI53CF92A LSI, LSI53CF92A Datasheet - Page 61

• Manufacturer Part Number: LSI53CF92A
• Manufacturer: LSI

Specifications of LSI53CF92A

• Lead Free Status / RoHS Status: Not Compliant

GE
PE
TC
Standard Register Set
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
Gross Error
This bit is set when one of the following occurs:
These conditions do not cause an interrupt; a gross error
may be detected only while servicing another interrupt.
This bit is cleared by reading the interrupt register if the
interrupt output is asserted. It is also cleared by a
hardware reset or the Reset command, but not SCSI reset.
Parity Error
This bit is set if parity checking is enabled in the
Configuration 1 (Config 1)
a SCSI parity error on command, data, status or
message bytes. Detected parity errors do not cause an
interrupt; they are merely reported with other
interrupt-causing events. If a parity error is detected
during an initiator Information In phase, ATN/ is
automatically asserted on the SCSI bus.
This bit is cleared by reading the
interrupt output is asserted. Hardware reset or the Reset
Chip command clears this bit, but not SCSI reset.
Terminal Count
This bit is set when the transfer counter decrements to
zero. It is not set by loading a zero into the
Transfer Counter
count is loaded. Because a DMA NOP (0x80) command
loads the
non-DMA NOP (00) does not load the counter and does
not clear this bit. Reading the Interrupt register does not
clear this bit. Hardware reset or the Reset Chip command
clears it, but SCSI reset does not.
The top of the FIFO is overwritten
The top of the
overwritten
Direction of DMA transfer is opposite to the direction
of the SCSI transfer
An unexpected phase change in initiator role during
Synchronous Data phase when the offset has not
been reconciled
Transfer
register, but resets when the transfer
Command
Counter, it also clears this bit. A
register and the FSC detects
register has been
Interrupt
register if the
4-11
6
5
4