LSI53CF92A LSI, LSI53CF92A Datasheet - Page 73

• Manufacturer Part Number: LSI53CF92A
• Manufacturer: LSI

Specifications of LSI53CF92A

• Lead Free Status / RoHS Status: Not Compliant

When transmitting to the SCSI bus, the FSC stops sending bytes when
it reaches this offset, and thereafter sends one byte for every
acknowledge it receives from the other SCSI device(s).
When receiving from the SCSI bus, the FSC sends an acknowledge
every time a byte is removed from its FIFO on the DMA interface. The
maximum offset of 15 allows a receiving FSC to store data in its FIFO
while the external DMA controller gains control of the memory bus. The
maximum offset is 15 for nonburst mode operation, and 7 for burst mode.
The synchronous offset is cleared (00) by hardware reset or a software
chip reset, but not SCSI reset.
Figure 4.1
Figure 4.1
Register Value
Register Value
Standard Register Set
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
Note: The input clock duty cycle affects the half clock
SYNC Offset
SYNC Offset
REQ/ ACK/
REQ/ ACK/
assertion/deassertion delays.
CLK
CLK
illustrates the REQ/ ACK/ deassertion delay.
REQ/ ACK/ Deassertion Delay
(Bits [5:4])
0 1 2 3
(Bits [5:4])
0 1 2 3
FASTCLK Enabled
FASTCLK Disabled
(Bits [7:6])
0 1 2 3
(Bits [7:6])
0 1 2 3
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