LSI53CF92A LSI, LSI53CF92A Datasheet - Page 113

• Manufacturer Part Number: LSI53CF92A
• Manufacturer: LSI

Specifications of LSI53CF92A

• Lead Free Status / RoHS Status: Not Compliant

5.5.8 Receive Message
5.5.9 Receive Command
5.5.10 Receive Data
5.5.11 Receive Command Sequence
This command causes the FSC to assert Message Out phase and
receive bytes from the initiator. For a non-DMA command, only one byte
per interrupt may be received. A DMA command interrupts after the
transfer counter decrements to zero. This command terminates by
generating a function complete interrupt.
This command causes the FSC to assert Command phase and receive
bytes from the initiator. For non-DMA Receive command, only one byte
per interrupt may be received. DMA Receive command interrupts after
the transfer counter decrements to zero. This command terminates by
generating a function complete interrupt.
This command causes the FSC to assert Data Out phase and receive
bytes from the initiator. For non-DMA Receive Data, only one byte per
interrupt may be received. DMA Receive Data interrupts after the transfer
counter decrements to zero and the FIFO is empty. This command
terminates by generating a function complete interrupt. DMA must be
used for synchronous transfers.
This command causes the FSC to assert Command phase and receive a
number of bytes, which vary according to the group code field of the first
byte. If the SCSI-2 bit is set in the
Group 2 commands are recognized as 10-byte commands. If the SCSI-2
bit is cleared, Group 2 commands are recognized as reserved
commands. Groups 3 and 4 are always reserved. The FSC requests six
bytes for reserved commands, six bytes for Group 6 vendor unique
commands, 10 bytes for Group 7 vendor unique commands, and 12 bytes
for Group 5 commands.
Target Command Group
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
Configuration 2 (Config 2)
register,
5-21