LSI53CF92A LSI, LSI53CF92A Datasheet - Page 56

• Manufacturer Part Number: LSI53CF92A
• Manufacturer: LSI

Specifications of LSI53CF92A

• Lead Free Status / RoHS Status: Not Compliant

4-6
With two exceptions, non-DMA commands do not use the counter.
During bus-initiated selection and during the Target Receive Command
sequence, the FSC decodes the group code field of the Command
Descriptor Block (CDB), loads the counter with the number of bytes in
the CDB, then decrements once for every byte received.
Registers
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
Target Decremented by
–
Initiator Decremented by
–
–
Note:
Data In phase
Synchronous Data In
Data Out
DMA Write, Multiplex Bus Mode DBWR/
DMA Write, Nonmultiplex Bus Mode DACK/
DMA Read, Multiplex Bus Mode DBRD/
DMA Read, Nonmultiplex Bus Mode DACK/
DMA Write, Multiplex Bus Mode DBWR/
DMA Write, Nonmultiplex Bus Mode DACK/
DACK/ can decrement the counter even if RD/ or WR/ do
not go true. False DACK/s can cause the counter to get out
of sync with the data stream, leading to subtle errors that
are difficult to trace. When false DACK/s are expected to
interfere with a temporarily suspended DMA operation, the
DREQ HIGH-Z bit in
set while the DMA is suspended.
Configuration 2 (Config 2)
should be