LSI53CF92A LSI, LSI53CF92A Datasheet - Page 151

• Manufacturer Part Number: LSI53CF92A
• Manufacturer: LSI

Specifications of LSI53CF92A

• Lead Free Status / RoHS Status: Not Compliant

A
asynchronous operation
B
bus configuration modes
bus initiated sequences
C
chip reset
clock conversion register
command register
command set
multiplexed
nonmultiplexed
bus initiated reselection
bus initiated reset
bus initiated selection
stacked commands
disconnect reset
hard reset
soft reset
clock conversion bits
command code bits
enable DMA bit
disconnected state command group
illegal commands
initiator command group
miscellaneous command group
disable selection/reselection
enable selection/reselection
reselect sequence
reselect3 sequence
select with ATN and stop sequence
select with ATN sequence
select with ATN3 sequence
select without ATN sequence
stacked commands
initiator command complete sequence
message accepted
reset ATN
set ATN
set ATN immediate
transfer information
transfer pad
flush FIFO
NOP
reset chip
reset SCSI bus
5-4
2-16
2-15
2-8
5-16
5-4
5-16
4-8
5-4
2-9
4-9
5-16
2-17
2-6
5-5
2-6
4-9
2-14
4-26
4-26
2-4
5-6
5-15
5-3
5-17
5-14
5-12
2-5
Index
LSI53CF92A Fast SCSI Controller
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
5-7
5-11
5-11
5-11
5-6
5-7
5-15
configuration 1 register
configuration 2 register
configuration 3 register
configuration 4 register
D
destination bus ID register
destination ID register
disconnect reset
DMA burst mode
DMA operation
target command group
chip test mode enable bit
enable parity checking bit
my bus ID bits
parity test mode bit
SCSI reset reporting disable interrupt bit
slow cable mode bit
DMA parity enable bit
DREQ High impedance bit
features enable bit
SCSI-2 bit
target bad parity abort bit
alternate DMA mode bit
CDB10 bit
fast SCSI bit
fastclk bit
ID message reserved check bit
queue tag enable bit
threshold eight bit
enable active negation bit
destination ID bits
deassertion of DREQ
DMA read
DMA write
DMA burst mode
DMA threshold
normal DMA mode
disconnect
disconnect sequence
receive command
receive command sequence
receive data
receive message
send data
send message
send status
target abort DMA
target command complete sequence
terminate sequence
4-32
2-12
4-29
4-31
2-13
2-17
4-31
2-11
5-18
5-20
4-25
2-9
5-18
5-21
2-11
4-33
4-13
4-13
5-18
4-28
2-9
4-24
4-28
4-30
4-34
4-24
4-24
5-21
4-31
5-22
2-12
5-21
4-30
5-19
4-32
5-19
4-25
4-30
4-25
4-35
4-28
4-30
5-21
5-20
4-24
IX-1