M41ST87WMX6 STMicroelectronics, M41ST87WMX6 Datasheet - Page 15

• Manufacturer Part Number: M41ST87WMX6
• Description: IC SUPERVISOR RTC 160X8 28-SOIC
• Manufacturer: STMicroelectronics
• Type: Clock/Calendar/Supervisorr

Specifications of M41ST87WMX6

• Memory Size: 160B
• Time Format: HH:MM:SS:hh (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC, 28-SOH (8.48mm Width)
• Function: Clock/Calendar/Alarm/Timer Interrupt
• Rtc Memory Size: 160 Byte
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Rtc Bus Interface: Serial (2-Wire, I2C)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-5370-5; M41ST87WMX6

M41ST87Y, M41ST87W
Table 2.
1. Valid for ambient operating temperature: T
2. Available in SOX28 (MX) package only.
3. Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling edge of SCL.
2.2
Note:
t
Symbol
HD:DAT
t
t
t
t
t
EXPD
SU:STO
HD:STA
SU:DAT
SU:STA
t
t
f
t
HIGH
LOW
SCL
BUF
t
t
R
F
(2)
(3)
AC characteristics
READ mode
In this mode the master reads the M41ST87Y/W slave after setting the slave address (see
Figure 9 on page
bit, the word address 'An' is written to the on-chip address pointer. Next the START condition
and slave address are repeated followed by the READ mode control bit (R/W=1). At this
point the master transmitter becomes the master receiver.
The data byte which was addressed will be transmitted and the master receiver will send an
acknowledge bit to the slave transmitter. The address pointer is only incremented on
reception of an acknowledge clock. The M41ST87Y/W slave transmitter will now place the
data byte at address An+1 on the bus, the master receiver reads and acknowledges the new
byte and the address pointer is incremented to An+2.
This cycle of reading consecutive addresses will continue until the master receiver sends a
STOP condition to the slave transmitter (see
The system-to-user transfer of clock data will be halted whenever the address being read is
a clock address (00h to 07h). The update will resume either due to a stop condition or when
the pointer increments to a non-clock or RAM address.
This is true both in READ mode and WRITE mode.
An alternate READ mode may also be implemented whereby the master reads the
M41ST87Y/W slave without first writing to the (volatile) address pointer. The first address
that is read is the last one stored in the pointer (see
SCL clock frequency
Time the bus must be free before a new transmission can start
EX to E
SDA and SCL fall time
Data hold time
START condition hold time
(after this period the first clock pulse is generated)
Clock high period
Clock low period
SDA and SCL rise time
Data setup time
START condition setup time
(only relevant for a repeated start condition)
STOP condition setup time
CON
propagation delay
16). Following the WRITE mode control bit (R/W=0) and the acknowledge
A
Parameter
= –40 to 85 °C; V
Doc ID 9497 Rev 9
(1)
CC
= 4.5 to 5.5 V or 2.7 to 3.6 V (except where noted).
Figure 10 on page
M41ST87W
M41ST87Y
Figure 11 on page
16).
Min
600
600
100
600
600
1.3
1.3
0
0
16).
Operating modes
Max
400
300
300
10
15
Unit
kHz
15/54
µs
ns
ns
ns
µs
ns
ns
µs
ns
ns
ns
ns