M41ST87WMX6 STMicroelectronics, M41ST87WMX6 Datasheet - Page 22

• Manufacturer Part Number: M41ST87WMX6
• Description: IC SUPERVISOR RTC 160X8 28-SOIC
• Manufacturer: STMicroelectronics
• Type: Clock/Calendar/Supervisorr

Specifications of M41ST87WMX6

• Memory Size: 160B
• Time Format: HH:MM:SS:hh (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC, 28-SOH (8.48mm Width)
• Function: Clock/Calendar/Alarm/Timer Interrupt
• Rtc Memory Size: 160 Byte
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Rtc Bus Interface: Serial (2-Wire, I2C)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-5370-5; M41ST87WMX6

Operating modes
2.6.6
Note:
2.6.7
2.6.8
2.6.9
Note:
Note:
22/54
Tamper detect sampling (TDS1 and TDS2)
This bit selects between a 1Hz sampling rate or constant monitoring of the tamper input
pin(s) to detect a tamper event when the normally closed switch mode is selected. This
allows the user to reduce the current drain when the TEB
in battery backup (see
if the TCM
“Don’t care.”
The crystal oscillator must be “on” for sampling to function. If the oscillator is stopped, the
tamper detect circuit will revert to continuous monitoring.
Tamper current high/tamper current low (TCHI/TCLO1 and
TCHI/TCLO2)
This bit selects the strength of the internal pull-up or pull-down used during the sampling of
the normally closed condition. The state of the TCHI/TCLO
open (TCM
RAM clear (CLR1 and CLR2)
When either CLR1 or CLR2 and the TEB
user RAM (see
condition. Furthermore, the 128 bytes of user RAM will be deselected (inaccessible) until
the corresponding TEB
the cleared RAM values cannot be accessed.)
RAM clear external (CLR1
package only
When either CLR1
the TP
upon detection of a tamper event (see
The reset output resulting from a tamper event will be the same as a reset resulting from a
power-down condition, a watchdog time-out, or a manual reset (RSTIN1 or RSTIN2); the
RST output will be asserted for t
This is accomplished by forcing TP
regulator (see
of power to the V
tamper occurs during battery back-up (see
regulator, the user will also prevent other inputs from sourcing current to the external SRAM,
which would allow it to retain data otherwise.
The user may optionally connect an inverting charge pump to the V
SRAM (see
manufacturing of the external SRAM, clearing the memory may require varying durations of
negative potential on the V
the time needed for their particular application. Control Bits CLRPW0 and CLRPW1
determine the duration TP
page
When using the inverting charge pump, the user must also provide isolation in the form of
two additional small-signal power MOSFETs. These will isolate the V
25).
CLR
X
signal will be asserted for clearing external RAM, and the RST output asserted
X
bit is set to logic '1' (Normally Open). In this case the state of the TDS
Figure 20 on page
= '1') mode (see
Figure 20 on page
Figure 15 on page
CC
EXT
pin. V
or CLR2
Table 4 on page 23
X
bit is reset to '0.' Any data read during this time will be invalid. (ie.
OUT
CLR
CC
Figure 18 on page
pin. This device configuration will allow the user to program
will automatically be disconnected from the battery if the
will be enabled (see
Doc ID 9497 Rev 9
EXT
25). Depending on the process technology used for the
rec
EXT
25) will also switch off V
CLR
21) will be cleared to all zeros in the event of a tamper
is set to a logic '1' and the TEB
seconds.
and CLR2
Figure 15 on page 21
high, which if used to control the inhibit pin of the DC
X
and
bit are set to a logic '1,' the internal 128 bytes of
Figure 19 on page
Figure 17 on page
24).
EXT
Figure 19 on page 24
) - available in SOX28
X
OUT
X
bit is enabled while the device is
bit is a “Don’t care” for normally
and
, depriving the external SRAM
24). By inhibiting the DC
Figure 20 on page
X
23). Sampling is disabled
M41ST87Y, M41ST87W
bit is also set to logic '1,'
CC
OUT
pin of the external
pin from both the
and
Table 5 on
X
bit is a
25).