GS8161Z36BGD-250 GSI TECHNOLOGY, GS8161Z36BGD-250 Datasheet - Page 12

• Manufacturer Part Number: GS8161Z36BGD-250
• Manufacturer: GSI TECHNOLOGY

Specifications of GS8161Z36BGD-250

• Density: 18Mb
• Access Time (max): 5.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 181MHz
• Operating Supply Voltage (typ): 2.5/3.3V
• Address Bus: 19b
• Package Type: FBGA
• Operating Temp Range: 0C to 70C
• Number Of Ports: 4
• Supply Current: 235mA
• Operating Supply Voltage (min): 2.3/3V
• Operating Supply Voltage (max): 2.7/3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 165
• Word Size: 36b
• Number Of Words: 512K
• Lead Free Status / Rohs Status: Compliant

Synchronous Truth Table
Rev: 1.05a 10/2009
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Read Cycle, Begin Burst
Read Cycle, Continue Burst
NOP/Read, Begin Burst
Dummy Read, Continue Burst
Write Cycle, Begin Burst
Write Abort, Begin Burst
Write Cycle, Continue Burst
Write Abort, Continue Burst
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Continue
Sleep Mode
Clock Edge Ignore, Stall
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. The address counter is incriminated for all Burst continue cycles.
Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Dese-
lect cycle is executed first.
Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W
pin is sampled low but no Byte Write pins are active so no write operation is performed.
G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during
write cycles.
If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.
signals are Low
All inputs, except G and ZZ must meet setup and hold times of rising clock edge.
Wait states can be inserted by setting CKE high.
This device contains circuitry that ensures all outputs are in High Z during power-up.
A 2-bit burst counter is incorporated.
X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write
Operation
Type Address CK CKE ADV W Bx E
W
R
B
R
B
D
B
B
D
D
D
D
External
External
External
Current
None
None
None
None
None
None
Next
Next
Next
Next
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
X
12/38
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
H
L
L
X
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
X
X
L
L
L
L
L
L
L
H
H
X
X
X
X
X
X
X
X
X
X
L
L
H
H
X
X
X
X
X
X
X
X
X
X
L
L
X
X
X
X
H
X
X
X
X
X
L
L
L
L
1
E
H
H
H
H
X
X
X
X
X
X
L
X
X
X
2
E
X
X
X
X
X
H
X
X
X
X
L
L
L
L
3
G ZZ
H
H
X
X
X
X
X
X
X
X
X
X
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
© 2004, GSI Technology
High-Z
High-Z
High-Z
High-Z 1,2,3,10
High-Z
High-Z
High-Z
High-Z
High-Z
DQ
Q
Q
D
D
-
Notes
1,2,10
1,3,10
1,10
2
3
1
1
4