GS8161Z36BGD-250 GSI TECHNOLOGY, GS8161Z36BGD-250 Datasheet - Page 32

• Manufacturer Part Number: GS8161Z36BGD-250
• Manufacturer: GSI TECHNOLOGY

Specifications of GS8161Z36BGD-250

• Density: 18Mb
• Access Time (max): 5.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 181MHz
• Operating Supply Voltage (typ): 2.5/3.3V
• Address Bus: 19b
• Package Type: FBGA
• Operating Temp Range: 0C to 70C
• Number Of Ports: 4
• Supply Current: 235mA
• Operating Supply Voltage (min): 2.3/3V
• Operating Supply Voltage (max): 2.7/3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 165
• Word Size: 36b
• Number Of Words: 512K
• Lead Free Status / Rohs Status: Compliant

JTAG Port Recommended Operating Conditions and DC Characteristics
JTAG Port AC Test Conditions
Notes:
1.
2.
Rev: 1.05a 10/2009
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Include scope and jig capacitance.
Test conditions as shown unless otherwise noted.
Input Under/overshoot voltage must be –2 V > Vi < V
V
0 V V
Output Disable, V
The TDO output driver is served by the V
I
I
I
I
OHJ
OLJ
OHJC
OHJC
ILJ
Output reference level
Input reference level
= + 4 mA
= –4 mA
 V
= –100 uA
= +100 uA
Input high level
Input slew rate
Input low level
Parameter
IN
IN
TMS, TCK and TDI Input Leakage Current
TMS, TCK and TDI Input Leakage Current
V
V
3.3 V Test Port Input High Voltage
2.5 V Test Port Input High Voltage
3.3 V Test Port Input Low Voltage
2.5 V Test Port Input Low Voltage
ILJn
TDO Output Leakage Current
Test Port Output High Voltage
Test Port Output Low Voltage
DDn
Test Port Output CMOS High
Test Port Output CMOS Low
OUT
= 0 to V
Parameter
DDn
DDQ
Conditions
V
supply.
DD
V
V
1 V/ns
0.2 V
DDQ
DDQ
– 0.2 V
/2
/2
DDn
32/38
+1.5 V maximum, with a pulse width not to exceed 50% tTKC.
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Symbol
V
V
V
V
V
V
V
I
V
I
I
INHJ
OHJC
INLJ
OLJC
OLJ
IHJ3
IHJ2
ILJ3
ILJ2
OHJ
OLJ
V
DDQ
DQ
0.6 * V
Min.
–300
–0.3
–0.3
– 100 mV
2.0
1.7
–1
–1
—
—
DD2
* Distributed Test Jig Capacitance
JTAG Port AC Test Load
0.3 * V
V
V
V
100 mV
DD3
DD2
Max.
DDQ
100
0.8
0.4
—
—
1
1
+0.3
+0.3
/2
DD2
50
© 2004, GSI Technology
Unit Notes
uA
uA
uA
V
V
V
V
V
V
V
V
30pF
*
5, 6
5, 7
5, 8
5, 9
1
1
1
1
2
3
4