GS8161Z36BGD-250 GSI TECHNOLOGY, GS8161Z36BGD-250 Datasheet - Page 29

• Manufacturer Part Number: GS8161Z36BGD-250
• Manufacturer: GSI TECHNOLOGY

Specifications of GS8161Z36BGD-250

• Density: 18Mb
• Access Time (max): 5.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 181MHz
• Operating Supply Voltage (typ): 2.5/3.3V
• Address Bus: 19b
• Package Type: FBGA
• Operating Temp Range: 0C to 70C
• Number Of Ports: 4
• Supply Current: 235mA
• Operating Supply Voltage (min): 2.3/3V
• Operating Supply Voltage (max): 2.7/3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 165
• Word Size: 36b
• Number Of Words: 512K
• Lead Free Status / Rohs Status: Compliant

Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
Instruction Descriptions
BYPASS
Rev: 1.05a 10/2009
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-
tate testing of other devices in the scan path.
1
0
Test Logic Reset
Run Test Idle
0
1
JTAG Tap Controller State Diagram
1
1
29/38
Capture DR
1
Update DR
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Pause DR
Select DR
Exit1 DR
Shift DR
Exit2 DR
0
0
1
1
0
1
0
1
0
0
0
1
1
Capture IR
1
Update IR
Pause IR
Select IR
Exit1 IR
Exit2 IR
Shift IR
0
1
1
0
1
0
0
© 2004, GSI Technology
1
0
0
0