GS8161Z36BGD-250 GSI TECHNOLOGY, GS8161Z36BGD-250 Datasheet - Page 18

• Manufacturer Part Number: GS8161Z36BGD-250
• Manufacturer: GSI TECHNOLOGY

Specifications of GS8161Z36BGD-250

• Density: 18Mb
• Access Time (max): 5.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 181MHz
• Operating Supply Voltage (typ): 2.5/3.3V
• Address Bus: 19b
• Package Type: FBGA
• Operating Temp Range: 0C to 70C
• Number Of Ports: 4
• Supply Current: 235mA
• Operating Supply Voltage (min): 2.3/3V
• Operating Supply Voltage (max): 2.7/3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 165
• Word Size: 36b
• Number Of Words: 512K
• Lead Free Status / Rohs Status: Compliant

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Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I
Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Designing for Compatibility
The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipelinemode via the FT signal found
on Pin 14. Not all vendors offer this option, however most mark Pin 14 as V
through parts. GSI NBT SRAMs are fully compatible with these sockets.
Rev: 1.05a 10/2009
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
CK
ZZ
SB
2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
tKC
tKC
tKH
tKH
Sleep Mode Timing Diagram
tKL
tKL
tZZS
18/38
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
tZZH
DD
or V
DDQ
on pipelined parts and V
tZZR
SB
© 2004, GSI Technology
2. The duration of
SS
on flow