GS8161Z36BGD-250 GSI TECHNOLOGY, GS8161Z36BGD-250 Datasheet - Page 16

• Manufacturer Part Number: GS8161Z36BGD-250
• Manufacturer: GSI TECHNOLOGY

Specifications of GS8161Z36BGD-250

• Density: 18Mb
• Access Time (max): 5.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 181MHz
• Operating Supply Voltage (typ): 2.5/3.3V
• Address Bus: 19b
• Package Type: FBGA
• Operating Temp Range: 0C to 70C
• Number Of Ports: 4
• Supply Current: 235mA
• Operating Supply Voltage (min): 2.3/3V
• Operating Supply Voltage (max): 2.7/3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 165
• Word Size: 36b
• Number Of Words: 512K
• Lead Free Status / Rohs Status: Compliant

Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.
Mode Pin Functions
Note:
There is a are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the ZZ pin, so thosethis input pins can be
unconnected and the chip will operate in the default states as specified in the above tables.
Rev: 1.05a 10/2009
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
FLXDrive Output Impedance Control
Single/Dual Cycle Deselect Control
Output Register Control
Power Down Control
Burst Order Control
Mode Name
9th Bit Enable
Pin Name
16/38
SCD
LBO
ZQ
FT
ZZ
PE
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
H or NC
H or NC
H or NC
L or NC
L or NC
State
H
H
H
L
L
L
L
Deactivate DQPx I/Os (x16/x3272 mode)
Activate DQPx I/Os (x18/x3672 mode)
High Drive (Low Impedance)
Low Drive (High Impedance)
Single Cycle Deselect
Dual Cycle Deselect
Standby, I
Interleaved Burst
Flow Through
Linear Burst
Function
Pipeline
Active
DD
© 2004, GSI Technology
= I
SB