EP2SGX60EF1152C3N Altera, EP2SGX60EF1152C3N Datasheet - Page 107

• Manufacturer Part Number: EP2SGX60EF1152C3N
• Description: IC STRATIX II GX 60K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX60EF1152C3N

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 534
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2181

Altera Corporation
October 2007
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Clock multiplication and division
Phase shift
Clock switchover
PLL reconfiguration
Reconfigurable bandwidth
Spread spectrum clocking
Programmable duty cycle
Number of internal clock outputs
Number of external clock outputs
Number of feedback clock inputs
Table 2–26. Stratix II GX PLL Features
For enhanced PLLs, m, n range from 1 to 256 and post-scale counters range from 1 to 512 with 50% duty cycle.
For fast PLLs, m, and post-scale counters range from 1 to 32. The n counter ranges from 1 to 4.
The smallest phase shift is determined by the voltage controlled oscillator (VCO) period divided by 8.
For degree increments, Stratix II GX devices can shift all output frequencies in increments of at least 45. Smaller
degree increments are possible depending on the frequency and divide parameters.
Stratix II GX fast PLLs only support manual clock switchover.
Fast PLLs can drive to any I/O pin as an external clock. For high-speed differential I/O pins, the device uses a data
channel to generate txclkout.
If the feedback input is used, you will lose one (or two, if f
Every Stratix II GX device has at least two enhanced PLLs with one single-ended or differential external feedback
input per PLL.
Table
Feature
2–26:
Table 2–26
devices.
Down to 125-ps increments (3),
Three differential/six single-ended
One single-ended or differential
m/(n × post-scale counter)
shows the enhanced PLL and fast PLL features in Stratix II GX
Enhanced PLL
(7),
v
v
v
v
v
6
(8)
BIN
is differential) external clock output pin.
(1)
Stratix II GX Device Handbook, Volume 1
(4)
Down to 125-ps increments (3),
m/(n × post-scale counter)
Stratix II GX Architecture
Fast PLL
v
v
v
v
(6)
4
(5)
(2)
2–99
(4)