EP2SGX60EF1152C3N Altera, EP2SGX60EF1152C3N Datasheet - Page 303

• Manufacturer Part Number: EP2SGX60EF1152C3N
• Description: IC STRATIX II GX 60K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX60EF1152C3N

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 534
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2181

(1)
Number of DQS Delay Buffer Stages
Table 4–114. DQS Phase-Shift Error Specifications for DLL-Delayed Clock (t
Delay stages used for request DQS phase shift are reported in a project’s Compilation Report in the Quartus II
software. For example, phase-shift error on two delay stages under -3 conditions is 50 ps peak-to-peak or 25 ps.
1
2
3
4
(1)
(2)
Number of DQS Delay Buffer Stages
Table 4–112. DLL Frequency Range Specifications (Part 2 of 2)
Table 4–113. DQS Jitter Specifications for DLL-Delayed Clock (t
Note (1)
Frequency Mode
Peak-to-peak period jitter on the phase-shifted DQS clock. For example, jitter on
two delay stages under commercial conditions is 200 ps peak-to-peak or 100 ps.
Delay stages used for requested DQS phase shift are reported in a project’s
Compilation Report in the Quartus II software.
(1)
3
–3 Speed Grade (ps) –4 Speed Grade (ps) –5 Speed Grade (ps)
(2)
1
2
3
4
100
25
50
75
240 to 350 (–4 and –5 speed grade)
240 to 400 (–3 speed grade)
Frequency Range (MHz)
Commercial (ps)
120
30
60
90
110
130
160
80
DQS
_
PSERR
)
Industrial (ps)
Resolution
(Degrees)
DQS
105
140
110
130
180
210
35
70
36
36
_
JITTER
)