EP2SGX60EF1152C3N Altera, EP2SGX60EF1152C3N Datasheet - Page 148

• Manufacturer Part Number: EP2SGX60EF1152C3N
• Description: IC STRATIX II GX 60K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX60EF1152C3N

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 534
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2181

High-Speed Differential I/O with DPA Support
Figure 2–89. Stratix II GX Receiver Channel
2–140
Stratix II GX Device Handbook, Volume 1
Up to 1 Gbps
Eight Phase Clocks
+
–
refclk
f
data
Fast
PLL
8
retimed_data
DPA
Figure 2–89
An external pin or global or regional clock can drive the fast PLLs, which
can output up to three clocks: two multiplied high-speed clocks to drive
the SERDES block and/or external pin, and a low-speed clock to drive the
logic array. In addition, eight phase-shifted clocks from the VCO can feed
to the DPA circuitry.
For more information on the fast PLL, see the
Devices
The eight phase-shifted clocks from the fast PLL feed to the DPA block.
The DPA block selects the closest phase to the center of the serial data eye
to sample the incoming data. This allows the source-synchronous
circuitry to capture incoming data correctly regardless of the
channel-to-channel or clock-to-channel skew. The DPA block locks to a
phase closest to the serial data phase. The phase-aligned DPA clock is
used to write the data into the synchronizer.
The synchronizer sits between the DPA block and the data realignment
and SERDES circuitry. Since every channel utilizing the DPA block can
have a different phase selected to sample the data, the synchronizer is
needed to synchronize the data to the high-speed clock domain of the
data realignment and the SERDES circuitry.
DPA_clk
chapter in volume 2 of the Stratix II GX Handbook.
Synchronizer
shows the block diagram of the Stratix II GX receiver channel.
diffioclk
load_en
D
Q
Data Realignment
Circuitry
Dedicated
Interface
Receiver
PLLs in Stratix II GX
Altera Corporation
Data to R4, R24, C4, or
direct link interconnect
Regional or
global clock
October 2007
10