EP2SGX60EF1152C3N Altera, EP2SGX60EF1152C3N Datasheet - Page 293

• Manufacturer Part Number: EP2SGX60EF1152C3N
• Description: IC STRATIX II GX 60K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX60EF1152C3N

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 534
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2181

(1)
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
1.8-V HSTL Class I
1.5-V HSTL Class I
LVDS
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
DDIO Column Output I/O
Table 4–101. Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path for -4 and -5
Devices
Table 4–102. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -3
Devices (Part 1 of 2)
Maximum DCD (ps) for
Maximum DCD (ps) for
Row DDIO Output I/O
Table 4–101
Standard
Standard
Note (1)
assumes the input clock has zero DCD.
Note (1)
3.3/2.5V
Therefore, the DCD percentage for the output clock is from 48.4% to
51.6%.
3.3/2.5V
260
210
195
150
255
175
170
155
440
390
375
325
430
355
350
335
330
330
180
TTL/CMOS
TTL/CMOS
Input IO Standard (No PLL in the Clock Path)
Input I/O Standard (No PLL in the Clock Path)
1.8/1.5V
1.8/1.5V
380
330
315
265
370
295
290
275
495
450
430
385
490
410
405
390
385
390
180
SSTL-2
SSTL-2
2.5V
145
100
140
85
85
2.5V
65
60
55
170
120
105
160
180
90
85
80
65
60
60
SSTL/HSTL
SSTL/HSTL
1.8/1.5V
1.8/1.5V
145
100
140
160
110
100
155
180
85
85
65
60
50
95
75
70
65
70
70
HSTL12
1.2V
145
100
140
85
85
65
60
50
LVDS
3.3V
105
135
100
105
110
105
180
75
90
85
90
Unit
ps
ps
ps
ps
ps
ps
ps
ps
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps