EP2SGX60EF1152C3N Altera, EP2SGX60EF1152C3N Datasheet - Page 99

• Manufacturer Part Number: EP2SGX60EF1152C3N
• Description: IC STRATIX II GX 60K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX60EF1152C3N

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 534
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2181

Figure 2–62. Regional Clocks
Altera Corporation
October 2007
CLK[3..0]
7
1
2
8
Dual-Regional Clock Network
A single source (CLK pin or PLL output) can generate a dual-regional
clock by driving two regional clock network lines in adjacent quadrants
(one from each quadrant), which allows logic that spans multiple
quadrants to utilize the same low skew clock. The routing of this clock
signal on an entire side has approximately the same speed but slightly
higher clock skew when compared with a clock signal that drives a single
quadrant. Internal logic-array routing can also drive a dual-regional
clock. Clock pins and enhanced PLL outputs on the top and bottom can
drive horizontal dual-regional clocks. Clock pins and fast PLL outputs on
the left and right can drive vertical dual-regional clocks, as shown in
Figure
RCLK
RCLK
[3..0]
[7..4]
2–63. Corner PLLs cannot drive dual-regional clocks.
[31..28]
[11..8]
RCLK
RCLK
CLK[15..12]
CLK[7..4]
11 5
12 6
[27..24]
[15..12]
RCLK
RCLK
Stratix II GX Device Handbook, Volume 1
[23..20]
[19..16]
RCLK
RCLK
Stratix II GX
Stratix II GX
Transceiver
Transceiver
Block
Block
Stratix II GX Architecture
2–91