EP2SGX60EF1152C3N Altera, EP2SGX60EF1152C3N Datasheet - Page 74

IC STRATIX II GX 60K 1152-FBGA

EP2SGX60EF1152C3N

Manufacturer Part Number
EP2SGX60EF1152C3N
Description
IC STRATIX II GX 60K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet

Specifications of EP2SGX60EF1152C3N

Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
534
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2181

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MultiTrack Interconnect
Figure 2–47. Shared Arithmetic Chain, Carry Chain and Register Chain Interconnects
2–66
Stratix II GX Device Handbook, Volume 1
Routing to Adjacent ALM
Carry Chain & Shared
The C4 interconnects span four LABs, M512, or M4K blocks up or down
from a source LAB. Every LAB has its own set of C4 interconnects to drive
either up or down.
from a LAB in a column. The C4 interconnects can drive and be driven by
all types of architecture blocks, including DSP blocks, TriMatrix memory
blocks, and column and row IOEs. For LAB interconnection, a primary
LAB or its LAB neighbor can drive a given C4 interconnect. C4
interconnects can drive each other to extend their range as well as drive
row interconnects for column-to-column connections.
Arithmetic Chain
Interconnect
Local
Figure 2–48
Local Interconnect
Routing Among ALMs
in the LAB
ALM 1
ALM 2
ALM 3
ALM 4
ALM 5
ALM 6
ALM 7
ALM 8
shows the C4 interconnect connections
Register Chain
Routing to Adjacent
ALM's Register Input
Altera Corporation
October 2007

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