EP2SGX60EF1152C3N Altera, EP2SGX60EF1152C3N Datasheet - Page 17

• Manufacturer Part Number: EP2SGX60EF1152C3N
• Description: IC STRATIX II GX 60K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX60EF1152C3N

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 534
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2181

Figure 2–6. 16-Bit to 20-Bit Encoding Process
Altera Corporation
October 2007
CTRL[1..0]
MSB
19
j'
h'
18
g'
17
15
H'
16
f'
14
G'
15
i'
13
F'
Figure 2–5. 8B/10B Encoding Process
In single-width mode, the 8B/10B encoder generates a 10-bit code group
from the 8-bit data and 1-bit control identifier. In double-width mode,
there are two 8B/10B encoders that are cascaded together and generate a
20-bit (2 × 10-bit) code group from the 16-bit (2 × 8-bit) data + 2-bit
(2 × 1-bit) control identifier.
process. The 8B/10B encoder conforms to the IEEE 802.3 1998 edition
standards.
Upon power on or reset, the 8B/10B encoder has a negative disparity
which chooses the 10-bit code from the RD-column. However, the
running disparity can be changed via the tx_forcedisp and
tx_dispval ports.
14
e'
12
E'
d'
13
11
D'
Cascaded 8B/10B Conversion
MSB sent last
12
c'
10
C'
11
b'
9
j
B'
9
a'
10
h
8
H
7
A'
8
g
7
9
G
j
6
H
7
Figure 2–6
8B/10B Conversion
h
6
8
5
F
f
G
6
E
g
5
4
7
Stratix II GX Device Handbook, Volume 1
i
F
5
3
D
6
e
4
f
shows the 20-bit encoding
E
4
2
C
5
i
d
3
D
3
B
1
e
4
c
2
C
2
Stratix II GX Architecture
0
A
d
3
LSB sent first
b
1
B
1
+
c
2
a
0
A
0
ctrl
Parallel Data
b
1
LSB
a
0
2–9