EP4CE55F23C6N Altera, EP4CE55F23C6N Datasheet - Page 136

• Manufacturer Part Number: EP4CE55F23C6N
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C6N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

6–28
Table 6–10. Cyclone IV GX HSSI REFCLK I/O Standard Support Using GPIO CLKIN Pins
LVDS I/O Standard Support in Cyclone IV Devices
Cyclone IV Device Handbook, Volume 1
Notes to
(1) The EP4CGX15, EP4CGX22, and EP4CGX30 devices have two pairs of dedicated clock input pins in banks 3A and 8A for HSSI input reference
(2) The EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150 devices have four pairs of dedicated clock input pins in banks 3A, 3B, 8A, and 8B
I/O Standard
3.3V PCML
1.2V, 1.5V,
LVPECL
LVDS
HCSL
clock. I/O banks 3B and 8B are not available in EP4CGX15, EP4CGX22, and EP4CGX30 devices.
for HSSI input or single-ended clock input.
Table
f
f
6–10:
HSSI Protocol
PCIe
For more information about the AC-coupled termination scheme for the HSSI
reference clock, refer to the
The LVDS I/O standard is a high-speed, low-voltage swing, low power, and GPIO
interface standard. Cyclone IV devices meet the ANSI/TIA/EIA-644 standard with
the following exceptions:
■
■
For LVDS I/O standard electrical specifications in Cyclone IV devices, refer to the
Cyclone IV Device Datasheet
Designing with LVDS
Cyclone IV I/O banks support the LVDS I/O standard. The Cyclone IV GX right I/O
banks support true LVDS transmitters while the Cyclone IV E left and right I/O banks
support true LVDS transmitters. On the top and bottom I/O banks, the emulated
LVDS transmitters are supported using two single-ended output buffers with external
resistors. One of the single-ended output buffers is programmed to have opposite
polarity. The LVDS receiver requires an external 100- termination resistor between
the two signals at the input buffer.
All
All
All
All
All
The maximum differential output voltage (V
maximum V
The input voltage range is reduced to the range of 1.0 V to 1.6 V, 0.5 V to 1.85 V, or
0 V to 1.8 V based on different frequency ranges. The ANSI/TIA/EIA-644
specification supports an input voltage range of 0 V to 2.4 V.
Differential
Differential
resistor to
AC (Need
Coupling
off chip
restore
V
DC
CM
OD
)
for ANSI specification is 450 mV.
Termination
Off chip
Off chip
Off chip
Off chip
Off chip
Off chip
chapter.
Cyclone IV Transceivers Architecture
Input
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
VCC_CLKIN Level
supported
supported
supported
supported
supported
supported
Output
Not
Not
Not
Not
Not
Not
OD
) is increased to 600 mV. The
Chapter 6: I/O Features in Cyclone IV Devices
(Note
Column
Yes
Yes
Yes
Yes
Yes
Yes
© December 2010 Altera Corporation
I/O
1),
High-Speed I/O Standards Support
chapter.
(2)
I/O Pin Type
Row
I/O
No
No
No
No
No
No
3A, 3B, 8A, 8B
3A, 3B, 8A, 8B
3A, 3B, 8A, 8B
3A, 3B, 8A, 8B
3A, 3B, 8A, 8B
3A, 3B, 8A, 8B
Supported I/O
Banks