EP4CE55F23C6N Altera, EP4CE55F23C6N Datasheet - Page 356

• Manufacturer Part Number: EP4CE55F23C6N
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C6N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

1–76
Self Test Modes
BIST
Figure 1–73. BIST Incremental Pattern Test Mode Datapath
Cyclone IV Device Handbook, Volume 2
Fabric
FPGA
1
Transmitter Channel PCS
Receiver Channel PCS
Pattern Generator
Transceiver
BIST Incremental
BIST Incremental
Pattern Verifier
Compensation
Each transceiver channel in the Cyclone IV GX device contains modules for pattern
generator and verifier. Using these built-in features, you can verify the functionality of
the functional blocks in the transceiver channel without requiring user logic. The self
test functionality is provided as an optional mechanism for debugging transceiver
channels.
There are three types of supported pattern generators and verifiers:
■
■
■
The self-test features are only supported in Basic mode.
Figure 1–73
incremental data generator and verifier are located near the FPGA fabric in the PCS
block of the transceiver channel.
FIFO
Rx
Built-in self test (BIST) incremental data generator and verifier—test the complete
transmitter PCS and receiver PCS datapaths for bit errors with parallel loopback
before the PMA blocks.
Pseudo-random binary sequence (PRBS) generator and verifier—the PRBS
generator and verifier interface with the serializer and deserializer in the PMA
blocks. The advantage of using a PRBS data stream is that the randomness yields
an environment that stresses the transmission medium. In the data stream, you
can observe both random jitter and deterministic jitter using a time interval
analyzer, bit error rate tester, or oscilloscope.
High frequency and low frequency pattern generator—the high frequency
patterns generate alternate ones and zeros and the low frequency patterns
generate five ones and five zeroes. These patterns do not have a corresponding
verifier.
Compensation
Tx Phase
FIFO
shows the datapath for BIST incremental data pattern test mode. The BIST
Ordering
Byte
Serializer
Byte
Deserial-
Byte
izer
Decoder
8B/10B
Encoder
8B/10B
Aligner
Word
Chapter 1: Cyclone IV Transceivers Architecture
loopback
Parallel
path
© December 2010 Altera Corporation
serializer
Transmitter Channel PMA
Serializer
Receiver Channel PMA
De-
Receiver
CDR
Self Test Modes