EP4CE55F23C6N Altera, EP4CE55F23C6N Datasheet - Page 304

• Manufacturer Part Number: EP4CE55F23C6N
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C6N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

1–24
Transceiver Clocking Architecture
Input Reference Clocking
Cyclone IV Device Handbook, Volume 2
1
The multipurpose PLLs and general-purpose PLLs located on the left side of the
device generate the clocks required for the transceiver operation. The following
sections describe the Cyclone IV GX transceiver clocking architecture:
■
■
■
When used for transceiver, the left PLLs synthesize the input reference clock to
generate the required clocks for the transceiver channels.
show the sources of input reference clocks for PLLs used in the transceiver operation.
Clock output from PLLs in the FPGA core cannot feed into PLLs used by the
transceiver as input reference clock.
Figure 1–25. PLL Input Reference Clocks in Transceiver Operation for F324 and Smaller Packages
Notes to
(1) The REFCLK0 and REFCLK1 pins are dual-purpose CLK, REFCLK, or DIFFCLK pins that reside in banks 3A and
(2) Using any clock input pins other than the designated REFCLK pins as shown here to drive the MPLLs may have
(Note
“Input Reference Clocking” on page 1–24
“Transceiver Channel Datapath Clocking” on page 1–26
“FPGA Fabric-Transceiver Interface Clocking” on page 1–39
8A respectively.
reduced jitter performance.
1),
Figure
(2)
1–25:
Transceiver
MPLL_2
MPLL_1
GXBL0
Block
REFCLK1
REFCLK0
Chapter 1: Cyclone IV Transceivers Architecture
Figure 1–25
© December 2010 Altera Corporation
Transceiver Clocking Architecture
and
Figure 1–26