EP4CE55F23C6N Altera, EP4CE55F23C6N Datasheet - Page 172

• Manufacturer Part Number: EP4CE55F23C6N
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C6N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

8–6
Configuration Process
Cyclone IV Device Handbook, Volume 1
f
f
This section describes Cyclone IV device configuration requirements and includes the
following topics:
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For more information about the Altera
to the
Power Up
If the device is powered up from the power-down state, V
the I/O banks in which the configuration and JTAG pins reside) must be powered up
to the appropriate level for the device to exit from POR.
Reset
After power up, Cyclone IV devices go through POR. POR delay depends on the
MSEL pin settings, which correspond to your configuration scheme. During POR, the
device resets, holds nSTATUS and CONF_DONE low, and tri-states all user I/O pins
(for PS and FPP configuration schemes only). To tri-state the configuration bus for AS
and AP configuration schemes, you must tie nCE high. The user I/O pins and
dual-purpose I/O pins have weak pull-up resistors, which are always enabled (after
POR) before and during configuration. When the device exits POR, all user I/O pins
continue to tri-state. While nCONFIG is low, the device is in reset. When nCONFIG
goes high, the device exits reset and releases the open-drain nSTATUS pin, which is
then pulled high by an external 10-k pull-up resistor. After nSTATUS is released, the
device is ready to receive configuration data and the configuration stage starts.
For more information about the value of the weak pull-up resistors on the I/O pins
that are on before and during configuration, refer to the
chapter.
Configuration
Configuration data is latched into the Cyclone IV device at each DCLK cycle. However,
the width of the data bus and the configuration time taken for each scheme are
different. After the device receives all the configuration data, the device releases the
open-drain CONF_DONE pin, which is pulled high by an external 10-kpull-up
resistor. A low-to-high transition on the CONF_DONE pin indicates that the
configuration is complete and initialization of the device can begin.
“Power Up” on page 8–6
“Reset” on page 8–6
“Configuration” on page 8–6
“Configuration Error” on page 8–7
“Initialization” on page 8–7
“User Mode” on page 8–7
Configuring Altera FPGAs
Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
chapter in volume 1 of the Configuration Handbook.
®
FPGA configuration cycle state machine, refer
Cyclone IV Device Datasheet
CCINT
© December 2010 Altera Corporation
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CCIO
Configuration
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