EP4CE55F23C6N Altera, EP4CE55F23C6N Datasheet - Page 38

• Manufacturer Part Number: EP4CE55F23C6N
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C6N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

3–2
Cyclone IV Device Handbook, Volume 1
f
Table 3–1
Table 3–1. Summary of M9K Memory Features
For information about the number of M9K memory blocks for Cyclone IV devices,
refer to the
Device Handbook.
Configurations (depth × width)
Parity bits
Byte enable
Packed mode
Address clock enable
Single-port mode
Simple dual-port mode
True dual-port mode
Embedded shift register mode
ROM mode
FIFO buffer
Simple dual-port mixed width support
True dual-port mixed width support
Memory initialization file (.mif)
Mixed-clock mode
Power-up condition
Register asynchronous clears
Latch asynchronous clears
Write or read operation triggering
Same-port read-during-write
Mixed-port read-during-write
Notes to
(1) FIFO buffers and embedded shift registers that require external logic elements (LEs) for implementing control
(2) Width modes of ×32 and ×36 are not available.
logic.
Table
lists the features supported by the M9K memory.
(1)
Cyclone IV Device Family Overview
3–1:
Feature
(1)
(2)
Read address registers and output registers only
Outputs set to Old Data or Don’t Care
chapter in volume 1 of the Cyclone IV
Outputs set to Old Data or New Data
Write and read: Rising clock edges
Chapter 3: Memory Blocks in Cyclone IV Devices
Output latches only
Outputs cleared
M9K Blocks
© November 2009 Altera Corporation
8192 × 1
4096 × 2
2048 × 4
1024 × 8
1024 × 9
512 × 16
512 × 18
256 × 32
256 × 36
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Overview