EP4CE55F23C6N Altera, EP4CE55F23C6N Datasheet - Page 210

• Manufacturer Part Number: EP4CE55F23C6N
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C6N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

8–44
Table 8–11. FPP Timing Parameters for Cyclone IV Devices (Part 2 of 2)
JTAG Configuration
Cyclone IV Device Handbook, Volume 1
Notes to
(1) This information is preliminary.
(2) Applicable for Cyclone IV GX and Cyclone IV E with 1.2-V core voltage.
(3) Applicable for Cyclone IV E with 1.0-V core voltage.
(4) This value is applicable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
(5) This value is applicable if you do not delay configuration by externally holding the nSTATUS low.
(6) The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for starting the device.
(7) Cyclone IV E devices with 1.0-V core voltage have slower F
t
t
t
t
t
t
t
t
t
f
ST2CK
DH
CD2UM
CD2CU
CD2UMC
DSU
CH
CL
CLK
MAX
Symbol
Table
8–11:
nSTATUS high to
first rising edge of
DCLK
Data hold time after
rising edge on
DCLK
CONF_DONE high
to user mode
CONF_DONE high
to CLKUSR
enabled
CONF_DONE high
to user mode with
CLKUSR option on
Data setup time
before rising edge
on DCLK
DCLK high time
DCLK low time
DCLK period
DCLK frequency
(7)
Parameter
JTAG has developed a specification for boundary-scan testing (BST). The BST
architecture offers the capability to efficiently test components on PCBs with tight
lead spacing. The BST architecture can test pin connections without using physical
test probes and capture functional data while a device is normally operating. You can
also use the JTAG circuitry to shift configuration data into the device. The Quartus II
software automatically generates .sof for JTAG configuration with a download cable
in the Quartus II software Programmer.
(6)
t
CD2CU
Cyclone IV
4 × maximum DCLK period
+ (3,192 × CLKUSR period)
3.2
3.2
7.5
—
5
(2)
Minimum
300
MAX
2
0
Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
when compared with Cyclone IV GX devices with 1.2-V core voltage.
Cyclone IV E
6.4
6.4
15
—
8
(3)
(Note 1)
Cyclone IV
133
—
—
—
—
(2)
Maximum
© December 2010 Altera Corporation
650
—
—
—
—
Cyclone IV E
—
—
—
—
66
(3)
Configuration
MHz
Unit
µs
ns
µs
—
—
ns
ns
ns
ns