EP4CE55F23C6N Altera, EP4CE55F23C6N Datasheet - Page 199

• Manufacturer Part Number: EP4CE55F23C6N
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C6N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Configuration
© December 2010 Altera Corporation
To ensure DCLK and DATA[0] are not left floating at the end of configuration, the
MAX II device must drive them either high or low, whichever is convenient on your
board. The DATA[0] pin is available as a user I/O pin after configuration. In the PS
scheme, the DATA[0] pin is tri-stated by default in user mode and must be driven by
the external host device. To change this default option in the Quartus II software,
select the Dual-Purpose Pins tab of the Device and Pin Options dialog box.
The configuration clock (DCLK) speed must be below the specified system frequency
to ensure correct configuration. No maximum DCLK period exists, which means you
can pause configuration by halting DCLK for an indefinite amount of time.
The external host device can also monitor CONF_DONE and INIT_DONE to ensure
successful configuration. The CONF_DONE pin must be monitored by the external
device to detect errors and to determine when programming is complete. If all
configuration data is sent, but CONF_DONE or INIT_DONE has not gone high, the
external device must reconfigure the target device.
Figure 8–14
This circuit is similar to the PS configuration circuit for a single device, except that
Cyclone IV devices are cascaded for multi-device configuration.
Figure 8–14. Multi-Device PS Configuration Using an External Host
Notes to
(1) The pull-up resistor must be connected to a supply that provides an acceptable input signal for all devices in the
(2) Connect the pull-up resistor to the V
(3) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.
(4) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect the MSEL pins,
(5) All I/O inputs must maintain a maximum AC voltage of 4.1 V. DATA[0] and DCLK must fit the maximum overshoot
(MAX II Device or
Microprocessor)
External Host
chain. V
refer to
to V
outlined in
ADDR
CCA
Figure
Memory
or GND.
Table 8–3 on page
CC
DATA[0]
must be high enough to meet the V
Equation 8–1 on page
shows how to configure multiple devices using an external host device.
8–14:
V
10 k
CCIO
(1) V
8–8,
10 k
Table 8–4 on page
CCIO
GND
8–5.
CCIO
(1)
Buffers (5)
supply voltage of the I/O bank in which the nCE pin resides.
CONF_DONE
DATA[0] (5)
nCONFIG
DCLK (5)
nCE
nSTATUS
Cyclone IV Device 1
IH
specification of the I/O on the device and the external host.
8–8, and
MSEL[ ]
nCEO
Table 8–5 on page
(4)
V
CCIO
Cyclone IV Device Handbook, Volume 1
8–9. Connect the MSEL pins directly
10 k
(2)
CONF_DONE
nCE
DATA[0] (5)
nCONFIG
nSTATUS
DCLK (5)
Cyclone IV Device 2
MSEL[ ]
nCEO
N.C. (3)
8–33
(4)