EP4CE55F23C6N Altera, EP4CE55F23C6N Datasheet - Page 206

• Manufacturer Part Number: EP4CE55F23C6N
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C6N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

8–40
Cyclone IV Device Handbook, Volume 1
1
Figure 8–19. Single-Device FPP Configuration Using an External Host
Notes to
(1) Connect the pull-up resistor to a supply that provides an acceptable input signal for the device. V
(2) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.
(3) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect the MSEL pins,
(4) All I/O inputs must maintain a maximum AC voltage of 4.1 V. DATA[7..0] and DCLK must fit the maximum
After nSTATUS is released, the device is ready to receive configuration data and the
configuration stage begins. When nSTATUS is pulled high, the external host device
places the configuration data one byte at a time on the DATA[7..0]pins.
Cyclone IV devices receive configuration data on the DATA[7..0] pins and the clock
is received on the DCLK pin. Data is latched into the device on the rising edge of DCLK.
Data is continuously clocked into the target device until CONF_DONE goes high. The
CONF_DONE pin goes high one byte early in FPP configuration mode. The last byte is
required for serial configuration (AS and PS) modes.
Two DCLK falling edges are required after CONF_DONE goes high to begin
initialization of the device.
Supplying a clock on CLKUSR does not affect the configuration process. After the
CONF_DONE pin goes high, CLKUSR is enabled after the time specified as t
this time period elapses, Cyclone IV devices require 3,192 clock cycles to initialize
properly and enter user mode. For more information about the supported CLKUSR
f
The INIT_DONE pin is released and pulled high when initialization is complete. The
external host device must be able to detect this low-to-high transition, which signals
the device has entered user mode. When initialization is complete, the device enters
user mode. In user mode, the user I/O pins no longer have weak pull-up resistors and
function as assigned in your design.
To ensure that DCLK and DATA[0] are not left floating at the end of the configuration,
the MAX II device must drive them either high or low, whichever is convenient on
your board. The DATA[0] pin is available as a user I/O pin after configuration. When
you choose the FPP scheme in the Quartus II software, the DATA[0] pin is tri-stated
by default in user mode and must be driven by the external host device. To change
this default option in the Quartus II software, select the Dual-Purpose Pins tab of the
Device and Pin Options dialog box.
MAX
enough to meet the V
refer to
overshoot outlined in
value for Cyclone IV devices, refer to
Figure
Table 8–4 on page 8–8
(MAX II Device or
Microprocessor)
8–19:
External Host
ADDR
IH
Equation 8–1 on page
specification of the I/O on the device and the external host.
Memory
DATA[7..0]
and
Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Table 8–5 on page
8–5.
10 k
V
CCIO
(1) V
10 k
Table 8–11 on page
8–9. Connect the MSEL pins directly to V
GND
CCIO
(1)
CONF_DONE
nSTATUS
nCE
nCONFIG
DCLK (4)
Cyclone IV Device
DATA[7..0] (4)
© December 2010 Altera Corporation
MSEL[3..0]
8–43.
nCEO
N.C. (2)
CCA
(3)
CC
CD2CU
must be high
or GND.
Configuration
. After