EP4CE55F23C6N Altera, EP4CE55F23C6N Datasheet - Page 312

• Manufacturer Part Number: EP4CE55F23C6N
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C6N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

1–32
Figure 1–35. Transmitter and Receiver Datapath Clocking with Rate Match FIFO in Non-Bonded Channel Configuration
Notes to
(1) Low-speed recovered clock.
(2) High-speed recovered clock.
Cyclone IV Device Handbook, Volume 2
Fabric
FPGA
tx_clkout
Figure 1–35
:
Figure 1–35
mode with the rate match FIFO. The receiver datapath clocking in configuration
without the rate match FIFO is identical to
In configuration with the rate match FIFO, the CDR unit in the receiver channel
recovers the clock from received serial data and generates the high-speed recovered
clock for the deserializer, and low-speed recovered clock for forwarding to the
receiver PCS. The low-speed recovered clock feeds to the following blocks in the
receiver PCS:
■
■
The low-speed clock that is used in the transmitter PCS datapath feeds the following
blocks in the receiver PCS:
■
■
■
■
■
When the byte deserializer is enabled, the low-speed clock frequency is halved before
feeding into the write clock of RX phase compensation FIFO. The low-speed clock is
available in the FPGA fabric as tx_clkout port, which can be used in the FPGA
fabric to send transmitter data and control signals, and capture receiver data and
status signals.
word aligner
write clock of rate match FIFO
read clock of rate match FIFO
8B/10B decoder
write clock of byte deserializer
byte ordering
write clock of RX phase compensation FIFO
Phase
Comp
FIFO
Rx
shows the datapath clocking in the transmitter and receiver operation
wr_clk
Tx Phase
Comp
FIFO
rd_clk
Order-
Byte
ing
/2
serializer
Byte
De-
wr_clk
Byte Serializer
/2
Transmitter Channel PCS
Decoder
8B/10B
rd_clk
Receiver Channel PCS
Figure
Match
Rate
FIFO
Chapter 1: Cyclone IV Transceivers Architecture
1–34.
8B/10B Encoder
Deskew
FIFO
© December 2010 Altera Corporation
(1)
Transceiver Clocking Architecture
Aligner
Word
Deserial-
Transmitter Channel PMA
Receiver Channel PMA
izer
Serializer
(2)
CDR
low-speed clock
high-speed
clock
CDR clock