20-668-0011 Rabbit Semiconductor, 20-668-0011 Datasheet - Page 41

IC MPU RABIT3000A 55.5MHZ128LQFP

20-668-0011

Manufacturer Part Number
20-668-0011
Description
IC MPU RABIT3000A 55.5MHZ128LQFP
Manufacturer
Rabbit Semiconductor
Datasheet

Specifications of 20-668-0011

Processor Type
Rabbit 3000 8-Bit
Speed
55.5MHz
Voltage
2.5V, 2.7V, 3V, 3.3V
Mounting Type
Surface Mount
Package / Case
128-LQFP
Data Bus Width
8 bit
Maximum Clock Frequency
55.5 MHz
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 55 C
Number Of Programmable I/os
56
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
316-1061

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
20-668-0011
Manufacturer:
Rabbit Semiconductor
Quantity:
10 000
4.2 Dependencies
4.2.1 I/O Pins
The CLK, STATUS, /WDTOUT, and /BUFEN pins are controlled by GOCR. Each of
these pins can be used as general-purpose outputs by driving them high or low:
• the CLK pin can output the peripheral clock, the peripheral clock divided by two, or be
• the STATUS pin can be active low during the first byte of each opcode fetch, active low
• the /WDTOUT pin can be active low whenever the watchdog timer resets the device or
• the /BUFEN pin can be active low during external I/O cycles, active low during data
The values in the battery-backed onchip-encryption RAM bytes are cleared If the signal
on the SMODE pins changes state.
4.2.2 Clocks
The periodic interrupt, real-time clock, watchdog timer, and secondary watchdog timer
require the 32 kHz clock.
4.2.3 Interrupts
The periodic interrupt is enabled in GCSR, and will occur every 488 µs. It is cleared by
reading GCSR. It can operate at Priority 1, 2, or 3.
The secondary watchdog interrupt will occur whenever the secondary watchdog is
enabled and allowed to count down to zero. It is cleared by restarting the secondary watch-
dog by writing to WDTCR. The secondary watchdog interrupt always occurs at Priority 3.
Chapter 4 System Management
driven high or low;
during an interrupt acknowledge, or driven high or low;
driven low; and
memory cycles, or driven high or low.
31

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