20-668-0011 Rabbit Semiconductor, 20-668-0011 Datasheet - Page 58
20-668-0011
Manufacturer Part Number
20-668-0011
Description
IC MPU RABIT3000A 55.5MHZ128LQFP
Manufacturer
Rabbit Semiconductor
Datasheet
1.20-668-0011.pdf
(312 pages)
Specifications of 20-668-0011
Processor Type
Rabbit 3000 8-Bit
Speed
55.5MHz
Voltage
2.5V, 2.7V, 3V, 3.3V
Mounting Type
Surface Mount
Package / Case
128-LQFP
Data Bus Width
8 bit
Maximum Clock Frequency
55.5 MHz
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 55 C
Number Of Programmable I/os
56
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
316-1061
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
20-668-0011
Manufacturer:
Rabbit Semiconductor
Quantity:
10 000
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5.4 Register Descriptions
48
Bit(s)
Bit(s)
* This bit is used only on the Rabbit 3000A and later versions; it is reserved and must be written
7:0
7
6
5
4
3
2
1
0
*
with zero on the Rabbit 3000.
MMU Instruction/Data Register
Stack Segment Register
Value
Value
Write
Read
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Internal I/O addresses are decoded using only the lower eight bits of the internal
I/O address bus. This restricts internal I/O addresses to the range 0x0000–
0x00FF.
Internal I/O addresses are decoded using all 15 bits of the address internal I/O
address bus. This option must be selected to access internal I/O addresses of
0x0100 and higher.
This bit is reserved and must be written with zero.
Enable A16 and A19 inversion independent of instruction/data.
Enable A16 and A19 inversion (controlled by bits 0-3) for data accesses only.
This enables the instruction/data split for the separate I and D space.
Normal /CS1 operation.
Force /CS1 always active. This will not cause any conflicts as long as the
memory using /CS1 does not also share an Output Enable or Write Enable with
another memory.
Normal operation.
For a DATASEG access, invert A19 before MBxCR (bank select) decision.
Normal operation.
For a data segment access: invert A16
Normal operation.
For root access, invert A19 before MBxCR (bank select) decision.
Normal operation.
For a root segment access: invert A16
The current contents of this register are reported.
Eight LSBs (MSBs are set to zero by write) of physical address offset to use if
SEGSIZ[7:4] Addr[15:12] < 0xE
(STACKSEG)
(MMIDR)
Description
Description
Rabbit 3000 Microprocessor User’s Manual
(Address = 0x0010)
(Address = 0x0011)
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