Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 18

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

I/O Interface Capabilities
PS011705-0608
Input
BRG
System communication to and from the SCC is performed through the SCC’s register set.
There are sixteen Write registers and eight Read registers.
Table 1
functions.
Throughout this document, Write and Read registers are referenced with the following
notation:
For example,
WR4A
RR3
•
•
RXD
DPLL
Upper Byte (WR13)
Time Constant
IN
‘WR’ for Write Register
‘RR’ for Read Register
16-Bit Down Counter
and
1-Bit
Write Register 4 for channel A
Read Register 3 for either/both channels
Table 2
DPLL
Internal TXD
Lower Byte (WR12)
MUX
Time Constant
Figure 7. SCC Receive Data Path
list the SCC registers and provide a brief description of their
DPLL
OUT
NRZI Decode
DIV 2
To Transmit Section
Internal Data Bus
SYNC Register
& Zero Delete
Output
BRG
CMOS SCC Serial Communications Controller
MUX
10 X 19 Frame
14-Bit Counter
Hunt Mode (BISYNC)
Status FIFO
SDLC-CRC
3-Bit
Rec. Error FIFO
Register (8 bits)
I/O Data buffer
3 Byte Deep
Receive Shift
CRC Delay
Register
CPU/I/O
Checker
CRC
Product Specification
CRC Result
SYNC
CRC
Rec. Error Logic
Rec. Error FIFO
3 Byte Deep
Functional Description
14