SPC5200CBV400B Freescale Semiconductor, SPC5200CBV400B Datasheet - Page 11

• Manufacturer Part Number: SPC5200CBV400B
• Description: IC MPU 32BIT 500MHZ 272PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC603er

Specifications of SPC5200CBV400B

• Processor Type: MPC52xx PowerPC 32-Bit
• Speed: 400MHz
• Voltage: 1.5V
• Mounting Type: Surface Mount
• Package / Case: 272-PBGA
• Core Size: 32 Bit
• Program Memory Size: 32KB
• Cpu Speed: 400MHz
• Embedded Interface Type: I2C, SPI, USB
• Digital Ic Case Style: BGA
• No. Of Pins: 272
• Rohs Compliant: No
• Family Name: MPC52xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

1.2.1
1.2.2
1.2.3
1.2.4
The internal clocking of the e300 core is generated from and synchronized to the system clock by means of a voltage-controlled
core PLL.
Freescale Semiconductor
1
2
3
The SYS_XTAL frequency and PLL Configuration bits must be chosen such that the resulting system frequency, CPU
(core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating
frequencies.
This represents total input jitter—short term and long term combined—and is guaranteed by design. Two different
types of jitter can exist on the input to CORE_SYSCLK, systemic and true random jitter. True random jitter is rejected.
Systemic jitter is passed into and through the PLL to the internal clock circuitry.
Relock time is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required
for the PLL lock after a stable VDD and CORE_SYSCLKare reached during the power-on reset sequence. This
specification also applies when the PLL has been disabled and subsequently re-enabled during sleep modes.
SYS_XTAL clock input jitter
System VCO frequency
System PLL relock time
Oscillator start-up time
SYS_XTAL frequency
RTC_XTAL frequency
SYS_XTAL frequency
SYS_XTAL cycle time
System Oscillator Electrical Characteristics
RTC Oscillator Electrical Characteristics
System PLL Electrical Characteristics
e300 Core PLL Electrical Characteristics
Characteristic
Characteristic
Characteristic
Table 8. System Oscillator Electrical Characteristics
Table 9. RTC Oscillator Electrical Characteristics
Table 10. System PLL Specifications
f
f
f
t
t
f
sys_xtal
sys_xtal
sys_xtal
VCOsys
up_osc
rtc_xtal
Sym
Sym
Sym
t
t
jitter
lock
MPC5200B Data Sheet, Rev. 4
Notes
Notes
Notes
(1)
(2)
(1)
(3)
(1)
15.6
15.6
66.6
Min
Min
Min
250
—
—
—
—
Typical
Typical
Typical
32.768
33.3
33.3
30.0
533
—
—
—
Max
35.0
Max
Max
35.0
28.5
150
800
100
10
—
MHz
MHz
MHz
Unit
Unit
Unit
kHz
ms
ns
ps
μs
SpecID
SpecID
SpecID
O1.1
O1.2
O2.1
O3.1
O3.2
O3.3
O3.4
O3.5
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