SPC5200CBV400B Freescale Semiconductor, SPC5200CBV400B Datasheet - Page 24

• Manufacturer Part Number: SPC5200CBV400B
• Description: IC MPU 32BIT 500MHZ 272PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC603er

Specifications of SPC5200CBV400B

• Processor Type: MPC52xx PowerPC 32-Bit
• Speed: 400MHz
• Voltage: 1.5V
• Mounting Type: Surface Mount
• Package / Case: 272-PBGA
• Core Size: 32 Bit
• Program Memory Size: 32KB
• Cpu Speed: 400MHz
• Embedded Interface Type: I2C, SPI, USB
• Digital Ic Case Style: BGA
• No. Of Pins: 272
• Rohs Compliant: No
• Family Name: MPC52xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

NOTES:
1. ACK can shorten the CS pulse width.
2. In Large Flash and MOST Graphics mode the shared PCI/ATA pins, used as address lines, are released at the same moment
3. ACK is input and can be used to shorten the CS pulse width.
4. Only available in Large Flash and MOST Graphics mode.
5. Only available in MOST Graphics mode.
6. Deadcycles are only used, if no arbitration to an other module (ATA or PCI) of the shared local bus happens. If arbitration
24
Wait States (WS) can be programmed in the Chip Select X Register, Bit field WaitP and WaitX. It can be specified from
0–65535.
as the CS. This can cause the address to change before CS is deasserted.
happens the bus can be driven within 4 IPB clocks by an other modules.
Sym
t
t
t
t
t
t
t
t
t
t
10
11
12
13
14
15
16
17
18
19
DATA input setup before CS negation
DATA input hold after CS negation
ACK assertion after CS assertion
TS assertion before CS assertion
ACK negation after CS negation
TSIZ valid before CS assertion
ACK change before PCI clock
TSIZ hold after CS negation
ACK change after PCI clock
TS pulse width
Description
Table 24. Non-MUXed Mode Timing (continued)
MPC5200B Data Sheet, Rev. 4
t
t
t
t
IPBIck
IPBIck
PCIck
PCIck
Min
8.5
—
—
—
—
0
(DC + 1) × t
t
t
Max
PCIck
PCIck
6.9
2.0
4.4
—
—
—
—
PCIck
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Freescale Semiconductor
Notes SpecID
—
(6)
(3)
(3)
(4)
(4)
(5)
(5)
(1)
(1)
A7.12
A7.13
A7.14
A7.15
A7.16
A7.17
A7.18
A7.19
A7.20
A7.21